Распиновка
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Исполнители
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Спонсор: розовые очки, черная маска и пара банок берна
Модуль moore — конечный автомат Moore
<Описание устройства> |
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Описание на Verilog (сгенерированный код) `timescale 1ns/1ns
module More ( clock,reset,ctrl, evnt);
input clock; input reset; input ctrl; tri0 reset; tri0 ctrl; output evnt; reg evnt; reg [4:0] fstate; reg [4:0] reg_fstate; parameter START=0,A=1,B=2,C=3,D=4;
always @(posedge clock or posedge reset) begin if (reset) begin fstate <= START; end else begin fstate <= reg_fstate; end end
always @(fstate or ctrl) begin evnt <= 1'b0; case (fstate) START: begin if (ctrl) reg_fstate <= A; else if (~(ctrl)) reg_fstate <= B; // Inserting 'else' block to prevent latch inference else reg_fstate <= START;
evnt <= 1'b1; end A: begin reg_fstate <= B;
evnt <= 1'b0; end B: begin if (ctrl) reg_fstate <= C; else if (~(ctrl)) reg_fstate <= D; // Inserting 'else' block to prevent latch inference else reg_fstate <= B;
evnt <= 1'b1; end C: begin if (ctrl) reg_fstate <= D; else if (~(ctrl)) reg_fstate <= A; // Inserting 'else' block to prevent latch inference else reg_fstate <= C;
evnt <= 1'b1; end D: begin if (ctrl) reg_fstate <= A; else if (~(ctrl)) reg_fstate <= C; // Inserting 'else' block to prevent latch inference else reg_fstate <= D;
evnt <= 1'b1; end default: begin evnt <= 1'bx; $display ("Reach undefined state"); end endcase end endmodule // AAAA |
RTL-схема
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States
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General
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Inputs
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Outputs
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Transition
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Action
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FSM-диаграмма
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Временная диаграмма
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