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E22FA КОНЕЧНЫЕ АВТОМАТЫ (FSM) |
ъыъ.рф/ЕыаЬ |
Исполнители: Модуль mealy — конечный автомат Mealy
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Описание на Verilog module mealy ( input clk, reset, ctrl, mng, output reg [3:0] evnt );
reg [2:0] state;
localparam START = 3'b000, A = 3'd001, B = 3'd010, C = 3'd011, D = 3'd100;
always@(posedge clk, negedge reset) begin if (~reset) state <= START; else case (state) START: if (ctrl) state <= A; else state <= B; A: if (ctrl) state <= B; else state <= B; B: if (ctrl) state <= C; else state <= D; C: if (ctrl) state <= D; else state <= A; D: if (ctrl) state <= A; else state <= C; default: state <= START; endcase end
always@(state) begin case (state) START: if (mng) evnt = 4'h0; else evnt = 4'h4; A: if (mng) evnt = 4'h1; else evnt = 4'h5; B: if (mng) evnt = 4'h2; else evnt = 4'h6; C: if (mng) evnt = 4'h3; else evnt = 4'h7; D: if (mng) evnt = 4'h4; else evnt = 4'h8; default: evnt = 4'h0; endcase end endmodule
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RTL-схема
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FSM-диаграмма
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Временная диаграмма
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* Модуль wrapper_mealy — обертка для конечного автомата Mealy
<Описание устройства> |
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Описание на Verilog module wrapper_mealy( input clk, input reset, input ctrl, input mng, output [6:0] seg );
wire [3:0] mealy_data;
mealy u_mealy( .clk(clk), .reset(reset), .ctrl(ctrl), .mng(mng), .evnt(mealy_data) );
driver7seg u_driver( .bin(mealy_data), .hex(seg) );
Endmodule
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RTL-схема
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