- •1 Features
- •2 Applications
- •3 Description
- •Table of Contents
- •4 Related Products
- •5 Pin Configuration Functions
- •6 Specifications
- •6.1 Absolute Maximum Ratings
- •6.2 ESD Ratings
- •6.3 Recommended Operating Conditions
- •6.4 Thermal Information
- •6.5 Electrical Characteristics
- •6.6 Typical Characteristics
- •7 Parameter Measurement Information
- •8 Application and Implementation
- •8.1 Application Information
- •8.1.1 Transimpedance Fundamentals
- •8.1.2 Noise Analysis
- •8.2 Typical Applications
- •8.2.1 Wideband Photodiode Transimpedance Amplifier
- •8.2.1.1 Detailed Design Procedure
- •8.2.1.1.1 Designing the Transimpedance Circuit
- •8.2.1.1.2 Measuring Transimpedance Bandwidth
- •8.2.1.1.3 Summary of Key Decisions in Transimpedance Design
- •8.2.1.1.4 Selection of Feedback Resistors
- •8.2.1.2 Application Curves
- •8.2.2 Alternative Transimpedance Configurations
- •8.3 Power Supply Recommendations
- •8.3.1 Slew-Rate Performance With Varying Input-Step Amplitude and Rise-and-Fall Time
- •8.4 Layout
- •8.4.1 Layout Guidelines
- •8.4.1.1 Printed-Circuit Board (PCB) Layout Techniques for High Performance
- •8.4.1.2 PowerPAD Design Considerations
- •8.4.1.3 PowerPAD PCB Layout Considerations
- •8.4.1.4 Power Dissipation and Thermal Considerations
- •8.4.2 Layout Example
- •9 Device and Documentation Support
- •9.1 Device Support
- •9.1.1 Design Tools Evaluation Fixture, Spice Models, and Applications Support
- •9.1.1.1 Bill of Materials
- •9.1.1.3 EVM Warnings and Restrictions
- •9.2 Documentation Support
- •9.2.1 Related Documentation
- •9.3 Receiving Notification of Documentation Updates
- •9.4 Support Resources
- •9.5 Trademarks
- •9.6 Electrostatic Discharge Caution
- •9.7 Glossary
- •10 Revision History
- •11 Mechanical, Packaging, and Orderable Information
THS4631
SLOS451C – DECEMBER 2004 – REVISED MARCH 2025 |
www.ti.com |
8.2.2 Alternative Transimpedance Configurations
Other transimpedance configurations are possible. The following three possibilities are shown.
The first configuration is a slight modification of the basic transimpedance circuit. By splitting the feedback resistor, the feedback capacitor value becomes more manageable and easier to control. This type of compensation scheme is useful when the feedback capacitor required in the basic configuration becomes so small that the parasitic effects of the board and components begin to dominate the total feedback capacitance. By reducing the resistance across the capacitor, the capacitor value can be increased. This compensation scheme mitigates the dominance of the parasitic effects.
|
CF |
RF1 |
RF2 |
λ |
_ |
|
+ |
RL |
|
−V(Bias)
Note: Splitting the feedback resistor enables use of a larger, more manageable feedback capacitor.
Figure 8-9. Alternative Transimpedance Configuration 1
The second configuration uses a resistive T-network to achieve high transimpedance gains using relatively small resistor values. This topology is useful when the desired transimpedance gain exceeds the value of available resistors. The transimpedance gain is given by Equation 7.
RE Q + RF 1 1 ) RF 2 RF 3
(7)
RF3 |
|
CF |
|
|
|
R |
F1 |
RF2 |
λ |
|
_ |
|
|
+ |
RL |
|
−V(Bias)
Note: A resistive T-network enables high transimpedance gain with reasonable resistor values.
Figure 8-10. Alternative Transimpedance Configuration 2
The third configuration uses a capacitive T-network to achieve fine control of the compensation capacitance. The capacitor CF3 can be used to tune the total effective feedback capacitance to a fine degree. This circuit behaves the same as the basic transimpedance configuration, with the effective CF given by Equation 8.
1 |
|
1 |
|
CF 3 |
|||
|
+ |
|
|
|
1 ) |
|
|
CF E Q |
CF 1 |
CF 2 |
|||||
|
|
|
|
|
(8) |
||
18 |
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