THS4631
SLOS451C – DECEMBER 2004 – REVISED MARCH 2025 www.ti.com
9.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
9.7 Glossary |
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TI Glossary |
This glossary lists and explains terms, acronyms, and definitions. |
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10 Revision History |
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NOTE: Page numbers for previous revisions may differ from page numbers in the current version. |
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Changes from Revision B (August 2011) to Revision C (March 2025) |
Page |
|
• Updated the numbering format for tables, figures, and cross-references throughout the document |
................. 1 |
|
• Added Device Information table......................................................................................................................... |
1 |
|
•Changed OPA656 Voltage Noise from 7nV/√Hz to 6nV/√Hz and Slew Rate from 290V/µs to 400V/µs in
Related FET-Input-Amplifier Products ............................................................................................................... |
2 |
• Added Pin Functions table.................................................................................................................................. |
2 |
• Moved ESD ratings from Absolute Maximum Ratings to new ESD Ratings...................................................... |
3 |
• Deleted 0°C to 70°C specifications from Electrical Characteristics.................................................................... |
4 |
• Changed 0.1dB bandwidth flatness, with 8.2pF feedback capacitor, from 38MHz to 6MHz (Typ)..................... |
4 |
• Added 0.1dB bandwidth flatness, with no 8.2pF feedback capacitor, with a value of 20MHz (Typ)................... |
4 |
•Changed Static output current (sourcing) from 80mA to 90mA (Min, –40°C to +125°C), 90mA to 120mA (Min,
25°C), 98mA to 180mA (Typ, 25°C)................................................................................................................... |
4 |
•Changed Static output current (sinking) from –80mA to –90mA (Max, –40°C to +125°C), –85mA to –120mA
(Max, 25°C), –95mA to –180mA (Typ, 25°C)..................................................................................................... |
4 |
•Changed Quiescent current from 13mA to 14.5mA (Max, 25°C) and 14mA to 15mA (Max, –40°C to +125°C) 4
• Updated graphs with new silicon data to the latest standard............................................................................. |
6 |
• Changed Input Voltage vs Frequency to Input Voltage and Current Noise vs Frequency ................................ |
6 |
• Added current noise data to Input Voltage and Current Noise vs Frequency ................................................... |
6 |
• Deleted Input Offset Current vs Temperature .................................................................................................... |
6 |
• Updated Input Bias Current vs Temperature to include input offset current....................................................... |
6 |
• Added typical CF = 0pF to Typical Characteristics operating conditions............................................................ |
6 |
Changes from Revision A (March 2005) to Revision B (August 2011) |
Page |
• Changed the Tstg value in the Absolute Maximum Ratings table From: 65°C to 150°C To: –65°C to 150°C.... 3 |
|
Changes from Revision * (December 2004) to Revision A (March 2005) |
Page |
• Changed the Related FET Input Amplifier Products table.................................................................................. |
1 |
• Changed the Differential input resistance value From: 109 || 6.5 To: 109 || 3.9................................................. |
4 |
• Changed the Common-mode input resistance value From: 109 || 6.5 To: 109 || 3.9......................................... |
4 |
• Changed Figure 8, Third Order Harmonic Distortion vs Frequency - From: RL = 499Ω To RF = 499Ω.............. |
6 |
• Changed Figure 9, Harmonic Distortion vs Output Voltage Swing - From: RL = 499Ω To RF = 499Ω............... |
6 |
• Added Figure 23, Large Signal Transient Response ......................................................................................... |
6 |
• Added Figure 24, Large Signal Transient Response ......................................................................................... |
6 |
• Added Figure 8-17, THS4631 EVM Schematic ............................................................................................... |
26 |
28 |
Submit Document Feedback |
Copyright © 2025 Texas Instruments Incorporated |
Product Folder Links: THS4631
www.ti.com |
THS4631 |
SLOS451C – DECEMBER 2004 – REVISED MARCH 2025 |
11 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2025 Texas Instruments Incorporated |
Submit Document Feedback |
29 |
|
Product Folder Links: THS4631 |
|
PACKAGE OPTION ADDENDUM
www.ti.com |
1-Nov-2025 |
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PACKAGING INFORMATION
Orderable part number |
Status |
Material type |
Package | Pins |
Package qty | Carrier |
RoHS |
Lead finish/ |
MSL rating/ |
Op temp (°C) |
Part marking |
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(1) |
(2) |
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(3) |
Ball material |
Peak reflow |
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(6) |
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(4) |
(5) |
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THS4631D |
Obsolete |
Production |
SOIC (D) | 8 |
- |
- |
Call TI |
Call TI |
-40 to 85 |
4631 |
THS4631DDA |
Active |
Production |
SO PowerPAD |
75 | TUBE |
Yes |
NIPDAU |
Level-2-260C-1 YEAR |
-40 to 85 |
4631 |
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(DDA) | 8 |
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THS4631DDA.A |
Active |
Production |
SO PowerPAD |
75 | TUBE |
Yes |
NIPDAU |
Level-2-260C-1 YEAR |
-40 to 85 |
4631 |
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(DDA) | 8 |
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THS4631DDA.B |
Active |
Production |
SO PowerPAD |
75 | TUBE |
Yes |
NIPDAU |
Level-2-260C-1 YEAR |
-40 to 85 |
4631 |
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(DDA) | 8 |
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THS4631DGN |
Obsolete |
Production |
HVSSOP (DGN) | 8 |
- |
- |
Call TI |
Call TI |
-40 to 85 |
ADK |
THS4631DGNR |
Active |
Production |
HVSSOP (DGN) | 8 |
2500 | LARGE T&R |
Yes |
NIPDAU | NIPDAUAG |
Level-2-260C-1 YEAR |
-40 to 85 |
ADK |
THS4631DGNR.A |
Active |
Production |
HVSSOP (DGN) | 8 |
2500 | LARGE T&R |
Yes |
NIPDAU |
Level-2-260C-1 YEAR |
-40 to 85 |
ADK |
THS4631DGNR.B |
Active |
Production |
HVSSOP (DGN) | 8 |
2500 | LARGE T&R |
Yes |
NIPDAU |
Level-2-260C-1 YEAR |
-40 to 85 |
ADK |
THS4631DR |
Active |
Production |
SOIC (D) | 8 |
2500 | LARGE T&R |
Yes |
NIPDAU |
Level-2-260C-1 YEAR |
-40 to 85 |
4631 |
THS4631DR.A |
Active |
Production |
SOIC (D) | 8 |
2500 | LARGE T&R |
Yes |
NIPDAU |
Level-2-260C-1 YEAR |
-40 to 85 |
4631 |
THS4631DR.B |
Active |
Production |
SOIC (D) | 8 |
2500 | LARGE T&R |
Yes |
NIPDAU |
Level-2-260C-1 YEAR |
-40 to 85 |
4631 |
(1)Status: For more details on status, see our product life cycle.
(2)Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind.
(3)RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition.
(4)Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width.
(5)MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board.
(6)Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com |
1-Nov-2025 |
|
|
Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceedthe total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
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PACKAGE MATERIALS INFORMATION |
www.ti.com |
8-Nov-2025 |
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TAPE AND REEL INFORMATION |
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REEL DIMENSIONS |
TAPE DIMENSIONS |
K0 |
P1 |
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B0 |
W |
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Reel |
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Diameter |
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Cavity |
A0 |
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A0 |
Dimension designed to accommodate the component width |
B0 |
Dimension designed to accommodate the component length |
K0 |
Dimension designed to accommodate the component thickness |
W |
Overall width of the carrier tape |
P1 |
Pitch between successive cavity centers |
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
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Q1 |
Q2 |
Q1 |
Q2 |
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Q3 |
Q4 |
Q3 |
Q4 |
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User Direction of Feed |
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Pocket Quadrants |
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*All dimensions are nominal |
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Device |
Package Package Pins |
SPQ |
Reel |
Reel |
A0 |
B0 |
K0 |
P1 |
W |
Pin1 |
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Type |
Drawing |
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Diameter |
Width |
(mm) |
(mm) |
(mm) |
(mm) |
(mm) |
Quadrant |
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(mm) |
W1 (mm) |
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THS4631DGNR |
HVSSOP |
DGN |
8 |
2500 |
330.0 |
12.4 |
5.3 |
3.4 |
1.4 |
8.0 |
12.0 |
Q1 |
THS4631DR |
SOIC |
D |
8 |
2500 |
330.0 |
12.4 |
6.4 |
5.2 |
2.1 |
8.0 |
12.0 |
Q1 |
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com |
8-Nov-2025 |
|
|
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
*All dimensions are nominal
Device |
Package Type |
Package Drawing |
Pins |
SPQ |
Length (mm) |
Width (mm) |
Height (mm) |
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THS4631DGNR |
HVSSOP |
DGN |
8 |
2500 |
353.0 |
353.0 |
32.0 |
THS4631DR |
SOIC |
D |
8 |
2500 |
353.0 |
353.0 |
32.0 |
Pack Materials-Page 2
|
GENERIC PACKAGE VIEW |
DGN 8 |
PowerPADTM HVSSOP - 1.1 mm max height |
3 x 3, 0.65 mm pitch |
SMALL OUTLINE PACKAGE |
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4225482/B
www.ti.com
|
PACKAGE OUTLINE |
DGN0008D |
PowerPADTM VSSOP - 1.1 mm max height |
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SMALL OUTLINE PACKAGE |
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C |
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A |
5.05 TYP |
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0.1 C |
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4.75 |
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PIN 1 INDEX AREA |
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SEATING |
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6X |
0.65 |
PLANE |
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8 |
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1 |
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3.1 |
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2X |
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1.95 |
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2.9 |
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NOTE 3 |
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4 |
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5 |
8X |
0.38 |
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3.1 |
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0.25 |
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B |
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0.13 |
C A B |
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2.9 |
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NOTE 4 |
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0.23 |
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0.13 |
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SEE DETAIL A |
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EXPOSED THERMAL PAD |
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4 |
5 |
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0.25 |
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1.89 |
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GAGE PLANE |
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9 |
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1.63 |
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1.1 MAX |
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1 |
8 |
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0.15 |
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0 -8 |
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0.7 |
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0.4 |
0.05 |
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1.57 |
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DETAIL A |
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TYPICAL |
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1.28 |
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4225481/A |
11/2019 |
NOTES: |
PowerPAD is a trademark of Texas Instruments. |
|
1.All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M.
2.This drawing is subject to change without notice.
3.This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side.
4.This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5.Reference JEDEC registration MO-187.
www.ti.com
|
EXAMPLE BOARD LAYOUT |
DGN0008D |
PowerPADTM VSSOP - 1.1 mm max height |
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SMALL OUTLINE PACKAGE |
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(2) |
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METAL COVERED |
NOTE 9 |
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BY SOLDER MASK |
(1.57) |
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SYMM |
SOLDER MASK |
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DEFINED PAD |
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8X (1.4) |
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(R0.05) TYP |
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8X (0.45) |
1 |
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8 |
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(3) |
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9 |
SYMM NOTE 9 |
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(1.89) |
6X (0.65) |
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(1.22) |
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5 |
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4 |
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( |
0.2) TYP |
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VIA |
(0.55) |
SEE DETAILS |
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(4.4) |
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LAND PATTERN EXAMPLE |
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EXPOSED METAL SHOWN |
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SCALE: 15X |
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SOLDER MASK |
METAL |
METAL UNDER |
SOLDER MASK |
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OPENING |
SOLDER MASK |
OPENING |
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EXPOSED METAL |
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EXPOSED METAL |
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0.05 MAX |
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0.05 MIN |
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ALL AROUND |
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ALL AROUND |
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NON-SOLDER MASK |
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SOLDER MASK |
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DEFINED |
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DEFINED |
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(PREFERRED) |
SOLDER MASK DETAILS |
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4225481/A |
11/2019 |
NOTES: (continued)
6.Publication IPC-7351 may have alternate designs.
7.Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8.Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented.
9.Size of metal pad may vary due to creepage requirement.
www.ti.com
|
EXAMPLE STENCIL DESIGN |
DGN0008D |
PowerPADTM VSSOP - 1.1 mm max height |
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SMALL OUTLINE PACKAGE |
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(1.57) |
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BASED ON |
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0.125 THICK |
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STENCIL |
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SYMM |
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8X (1.4) |
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(R0.05) TYP |
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8X (0.45) |
1 |
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8 |
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SYMM |
(1.89) |
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BASED ON |
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0.125 THICK |
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STENCIL |
6X (0.65) |
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4 |
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5 |
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METAL COVERED |
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SEE TABLE FOR |
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BY SOLDER MASK |
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DIFFERENT OPENINGS |
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(4.4) |
FOR OTHER STENCIL |
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THICKNESSES |
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SOLDER PASTE EXAMPLE |
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EXPOSED PAD 9: |
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100% PRINTED SOLDER COVERAGE BY AREA |
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SCALE: 15X |
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STENCIL |
SOLDER STENCIL |
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THICKNESS |
OPENING |
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0.1 |
1.76 X 2.11 |
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0.125 |
1.57 X 1.89 (SHOWN) |
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0.15 |
1.43 X 1.73 |
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0.175 |
1.33 X 1.60 |
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4225481/A 11/2019
NOTES: (continued)
10.Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations.
11.Board assembly site may have different recommendations for stencil design.
www.ti.com
|
PACKAGE OUTLINE |
DGN0008H |
PowerPADTM VSSOP - 1.1 mm max height |
|
SMALL OUTLINE PACKAGE |
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C |
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A |
5.05 TYP |
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0.1 C |
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4.75 |
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PIN 1 INDEX AREA |
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SEATING |
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6X |
0.65 |
PLANE |
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8 |
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1 |
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3.1 |
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2X |
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1.95 |
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2.9 |
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NOTE 3 |
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4 |
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5 |
8X |
0.38 |
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3.1 |
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0.25 |
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B |
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0.13 |
C A B |
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2.9 |
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NOTE 4 |
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0.23 |
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0.13 |
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SEE DETAIL A |
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(0.205) MAX |
(0.48) MAX |
EXPOSED THERMAL PAD |
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NOTE 6 |
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NOTE 6 |
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4 |
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5 |
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0.25 |
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1.8 |
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GAGE PLANE |
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9 |
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1.1 |
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1.1 MAX |
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1 |
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8 |
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0.15 |
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0 -8 |
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0.7 |
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0.05 |
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0.4 |
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1.71 |
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DETAIL A |
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TYPICAL |
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1.01 |
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4229130/B |
05/2024 |
NOTES: |
PowerPAD is a trademark of Texas Instruments. |
|
1.All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M.
2.This drawing is subject to change without notice.
3.This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side.
4.This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5.Reference JEDEC registration MO-187.
6.Features may differ or may not be present.
www.ti.com
|
EXAMPLE BOARD LAYOUT |
DGN0008H |
PowerPADTM VSSOP - 1.1 mm max height |
|
SMALL OUTLINE PACKAGE |
|
|
(2) |
|
|
|
METAL COVERED |
NOTE 10 |
|
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|
|
BY SOLDER MASK |
(1.71) |
|
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SYMM |
SOLDER MASK |
|
|
|
DEFINED PAD |
|
|
|
8X (1.4) |
|
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|
|
(R0.05) TYP |
||
8X (0.45) |
1 |
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8 |
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||
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(3) |
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9 |
SYMM |
NOTE 10 |
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(1.8) |
6X (0.65) |
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(1.22) |
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5 |
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4 |
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( |
0.2) TYP |
|
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VIA |
(0.55) |
SEE DETAILS |
|
|
|
(4.4) |
|
|
|
|
LAND PATTERN EXAMPLE |
|
|
|
|
EXPOSED METAL SHOWN |
|
|
|
|
SCALE: 15X |
|
|
SOLDER MASK |
METAL |
METAL UNDER |
SOLDER MASK |
|
|
OPENING |
SOLDER MASK |
OPENING |
|
||
|
|
|
|||
EXPOSED METAL |
|
|
|
EXPOSED METAL |
|
|
0.05 MAX |
|
|
0.05 MIN |
|
|
ALL AROUND |
|
|
ALL AROUND |
|
NON-SOLDER MASK |
|
|
SOLDER MASK |
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|
DEFINED |
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DEFINED |
|
|
(PREFERRED) |
SOLDER MASK DETAILS |
|
|||
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||||
|
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||
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|
|
4229130/B |
05/2024 |
NOTES: (continued)
7.Publication IPC-7351 may have alternate designs.
8.Solder mask tolerances between and around signal pads can vary based on board fabrication site.
9.Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented.
10.Size of metal pad may vary due to creepage requirement.
www.ti.com
|
EXAMPLE STENCIL DESIGN |
DGN0008H |
PowerPADTM VSSOP - 1.1 mm max height |
|
SMALL OUTLINE PACKAGE |
8X (1.4) 
8X (0.45) |
1 |
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6X (0.65)
4 
METAL COVERED
BY SOLDER MASK
(1.71) |
|
|
BASED ON |
|
|
0.125 THICK |
|
|
STENCIL |
|
|
SYMM |
|
|
(R0.05) TYP |
||
8 |
|
|
SYMM |
(1.8) |
|
BASED ON |
||
|
||
|
0.125 THICK |
|
|
STENCIL |
|
|
5 |
|
SEE TABLE FOR |
(4.4) |
DIFFERENT OPENINGS |
FOR OTHER STENCIL |
|
|
THICKNESSES |
SOLDER PASTE EXAMPLE
EXPOSED PAD 9:
100% PRINTED SOLDER COVERAGE BY AREA
SCALE: 15X
STENCIL |
SOLDER STENCIL |
THICKNESS |
OPENING |
|
|
0.1 |
1.91 X 2.01 |
0.125 |
1.71 X 1.80 (SHOWN) |
0.15 |
1.56 X 1.64 |
0.175 |
1.45 X 1.52 |
4229130/B 05/2024
NOTES: (continued)
11.Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations.
12.Board assembly site may have different recommendations for stencil design.
www.ti.com
|
PACKAGE OUTLINE |
DGN0008G |
PowerPADTM HVSSOP - 1.1 mm max height |
|
SMALL OUTLINE PACKAGE |
|
|
|
|
|
C |
|
A |
5.05 TYP |
|
|
|
0.1 C |
|
|
4.75 |
|
|
|
|
|
|
PIN 1 INDEX AREA |
|
|
|
SEATING |
|
|
|
6X |
0.65 |
PLANE |
||
|
8 |
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|||
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1 |
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3.1 |
|
2X |
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||
|
1.95 |
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|||
2.9 |
|
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|||
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NOTE 3 |
|
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4 |
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5 |
8X |
0.38 |
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|||
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3.1 |
|
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0.25 |
|
|
B |
|
|
0.13 |
C A B |
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2.9 |
|
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NOTE 4 |
|
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0.23 |
|
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|
0.13 |
|
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|
|
SEE DETAIL A |
|
|
|
|
|
|
EXPOSED THERMAL PAD |
|
|
|||
4 |
5 |
|
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|
|
|
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|
|
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|
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|
|
0.25 |
|
|
2.15 |
|
|
|
GAGE PLANE |
|
|
9 |
|
|
|
|
|
|
1.95 |
|
|
|
1.1 MAX |
||
|
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|
||
1 |
8 |
|
|
|
|
0.15 |
|
0 -8 |
|
|
0.7 |
||
|
|
|
|
0.4 |
0.05 |
|
|
1.846 |
|
|
|
DETAIL A |
|
|
|
|
|
TYPICAL |
|
|
|
1.646 |
|
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|
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|
|
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|
|
4225480/C |
11/2024 |
NOTES: |
PowerPAD is a trademark of Texas Instruments. |
|
1.All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M.
2.This drawing is subject to change without notice.
3.This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side.
4.This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5.Reference JEDEC registration MO-187.
www.ti.com
|
EXAMPLE BOARD LAYOUT |
DGN0008G |
PowerPADTM HVSSOP - 1.1 mm max height |
|
SMALL OUTLINE PACKAGE |
|
|
(2) |
|
|
METAL COVERED |
NOTE 9 |
|
|
|
|
|
|
BY SOLDER MASK |
(1.57) |
|
|
|
SYMM |
SOLDER MASK |
|
|
DEFINED PAD |
|
|
8X (1.4) |
|
|
|
|
(R0.05) TYP |
|
8X (0.45) |
1 |
|
8 |
|
|
||
|
|
|
(3) |
|
|
9 |
SYMM NOTE 9 |
|
|
|
|
|
|
|
(1.89) |
6X (0.65) |
|
(1.22) |
|
|
|
|
5 |
|
4 |
|
|
( |
0.2) TYP |
|
|
|
VIA |
(0.55) |
SEE DETAILS |
|
|
(4.4) |
|
|
|
LAND PATTERN EXAMPLE |
|
|
|
EXPOSED METAL SHOWN |
|
|
|
SCALE: 15X |
|
SOLDER MASK |
METAL |
METAL UNDER |
SOLDER MASK |
|
|
OPENING |
SOLDER MASK |
OPENING |
|
||
|
|
|
|||
EXPOSED METAL |
|
|
|
EXPOSED METAL |
|
|
0.05 MAX |
|
|
0.05 MIN |
|
|
ALL AROUND |
|
|
ALL AROUND |
|
NON-SOLDER MASK |
|
|
SOLDER MASK |
|
|
|
DEFINED |
|
|
|
|
|
|
|
DEFINED |
|
|
(PREFERRED) |
SOLDER MASK DETAILS |
|
|||
|
|
||||
|
|
|
|
||
|
|
|
|
4225480/C |
11/2024 |
NOTES: (continued)
6.Publication IPC-7351 may have alternate designs.
7.Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8.Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented.
9.Size of metal pad may vary due to creepage requirement.
www.ti.com
|
EXAMPLE STENCIL DESIGN |
DGN0008G |
PowerPADTM HVSSOP - 1.1 mm max height |
|
SMALL OUTLINE PACKAGE |
|
|
(1.57) |
|
|
|
|
BASED ON |
|
|
|
|
0.125 THICK |
|
|
|
|
STENCIL |
|
|
|
|
SYMM |
|
|
|
8X (1.4) |
|
(R0.05) TYP |
|
8X (0.45) |
1 |
|
8 |
|
|
|
|
||
|
|
|
SYMM |
(1.89) |
|
|
|
BASED ON |
|
|
|
|
|
|
|
|
|
|
0.125 THICK |
|
|
|
|
STENCIL |
6X (0.65) |
|
|
|
|
|
4 |
|
5 |
|
METAL COVERED |
|
SEE TABLE FOR |
||
BY SOLDER MASK |
(4.4) |
DIFFERENT OPENINGS |
||
|
|
FOR OTHER STENCIL |
||
|
|
|
THICKNESSES |
|
|
SOLDER PASTE EXAMPLE |
|
|
|
|
EXPOSED PAD 9: |
|
|
|
|
100% PRINTED SOLDER COVERAGE BY AREA |
|
|
|
|
|
SCALE: 15X |
|
|
|
STENCIL |
SOLDER STENCIL |
|
|
|
THICKNESS |
OPENING |
|
|
|
0.1 |
1.76 X 2.11 |
|
|
|
0.125 |
1.57 X 1.89 (SHOWN) |
|
|
|
0.15 |
1.43 X 1.73 |
|
|
|
0.175 |
1.33 X 1.60 |
|
|
4225480/C 11/2024
NOTES: (continued)
10.Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations.
11.Board assembly site may have different recommendations for stencil design.
www.ti.com
|
GENERIC PACKAGE VIEW |
DDA 8 |
PowerPAD TM SOIC - 1.7 mm max height |
|
PLASTIC SMALL OUTLINE |
Images above are just a representation of the package family, actual package may vary. Refer to the product data sheet for package details.
4202561/G
|
PACKAGE OUTLINE |
DDA0008B |
PowerPAD TM SOIC - 1.7 mm max height |
|
PLASTIC SMALL OUTLINE |
|
6.2 |
|
|
|
|
C |
|
|
|
|
|
|
SEATING PLANE |
|
|
A |
5.8 TYP |
|
|
|
|
|
|
PIN 1 ID |
|
|
|
|
|
|
|
|
|
|
|
|
0.1 C |
|
|
|
AREA |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
8 |
6X |
1.27 |
|
|
|
1 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
5.0 |
|
|
2X |
|
|
|
|
4.8 |
|
3.81 |
|
|
|
||
NOTE 3 |
|
|
|
|
|
|
|
4 |
|
|
|
|
|
4X (0 -10 ) |
|
|
|
|
|
|
|
|
|
|
|
5 |
0.51 |
|
|
|
|
|
|
8X |
|
|
|
||
B |
4.0 |
|
0.31 |
|
1.7 MAX |
|
|
|
0.25 |
C A B |
|
||||
|
3.8 |
|
|
|
|||
|
NOTE 4 |
|
|
|
|
|
|
|
|
0.25 |
TYP |
|
|
|
|
|
|
0.10 |
|
|
|
||
|
SEE DETAIL A |
|
|
|
|
|
|
4 |
|
5 |
|
|
|
|
|
|
|
EXPOSED |
|
|
|
||
|
|
THERMAL PAD |
|
|
|||
3.4 |
9 |
|
|
|
|
0.25 |
|
|
|
GAGE PLANE |
|
||||
2.8 |
|
|
|
||||
|
|
|
|
||||
|
|
|
|
|
|
|
0.15 |
1 |
|
8 |
|
|
0 - 8 |
1.27 |
0.00 |
|
|
|
|
0.40 |
|
||
|
|
|
|
|
|
|
|
|
2.71 |
|
|
|
|
DETAIL A |
|
|
|
|
|
|
TYPICAL |
|
|
|
2.11 |
|
|
|
|
|
|
|
|
|
|
|
|
4214849/B |
09/2025 |
NOTES: |
PowerPAD is a trademark of Texas Instruments. |
|
1.All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M.
2.This drawing is subject to change without notice.
3.This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side.
4.This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5.Reference JEDEC registration MS-012.
www.ti.com
|
EXAMPLE BOARD LAYOUT |
DDA0008B |
PowerPAD TM SOIC - 1.7 mm max height |
|
PLASTIC SMALL OUTLINE |
|
(2.95) |
|
|
|
NOTE 9 |
SOLDER MASK |
|
|
(2.71) |
|
|
|
DEFINED PAD |
|
|
|
SOLDER MASK |
|
|
|
|
|
|
8X (1.55) |
OPENING |
SEE DETAILS |
|
|
|||
|
|
|
|
1 |
|
|
|
|
|
8 |
|
8X (0.6) |
|
|
|
SYMM |
9 |
|
(3.4) |
(1.3) |
SOLDER MASK |
||
|
|
TYP |
OPENING |
|
|
|
(4.9) |
6X (1.27) |
|
|
NOTE 9 |
|
|
|
|
4 |
|
5 |
|
|
|
|
|
(R0.05) TYP |
|
|
|
( 0.2) TYP |
SYMM |
METAL COVERED |
|
|
BY SOLDER MASK |
||
VIA |
|
||
|
|
|
|
|
(1.3) TYP |
|
|
|
(5.4) |
|
|
|
LAND PATTERN EXAMPLE |
|
|
|
SCALE:10X |
|
|
|
0.07 MAX |
0.07 MIN |
|
|
ALL AROUND |
ALL AROUND |
|
SOLDER MASK |
METAL |
SOLDER MASK |
METAL UNDER |
OPENING |
|
OPENING |
SOLDER MASK |
NON SOLDER MASK |
SOLDER MASK |
DEFINED |
DEFINED |
SOLDER MASK DETAILS
PADS 1-8
4214849/B 09/2025
NOTES: (continued)
6.Publication IPC-7351 may have alternate designs.
7.Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8.This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).
9.Size of metal pad may vary due to creepage requirement.
10.Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
|
EXAMPLE STENCIL DESIGN |
DDA0008B |
PowerPADTM SOIC - 1.7 mm max height |
|
PLASTIC SMALL OUTLINE |
|
(2.71) |
|
|
|
BASED ON |
|
|
|
0.125 THICK |
|
|
8X (1.55) |
STENCIL |
(R0.05) TYP |
|
|
|||
|
1 |
||
|
|
||
|
|
8 |
|
8X (0.6) |
|
|
|
|
|
(3.4) |
|
SYMM |
9 |
BASED ON |
|
|
|
0.125 THICK |
|
|
|
STENCIL |
|
6X (1.27) |
|
|
|
|
4 |
5 |
|
|
|
||
METAL COVERED |
SYMM |
SEE TABLE FOR |
|
BY SOLDER MASK |
|||
|
|||
|
|
DIFFERENT OPENINGS |
|
|
(5.4) |
FOR OTHER STENCIL |
|
|
THICKNESSES |
||
|
|
||
|
SOLDER PASTE EXAMPLE |
|
|
|
EXPOSED PAD |
|
|
|
100% PRINTED SOLDER COVERAGE BY AREA |
|
|
|
SCALE:10X |
|
STENCIL |
SOLDER STENCIL |
THICKNESS |
OPENING |
|
|
0.1 |
3.03 X 3.80 |
0.125 |
2.71 X 3.40 (SHOWN) |
0.150 |
2.47 X 3.10 |
0.175 |
2.29 X 2.87 |
4214849/B 09/2025
NOTES: (continued)
11.Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations.
12.Board assembly site may have different recommendations for stencil design.
www.ti.com
|
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PACKAGE OUTLINE |
D0008A |
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SOIC - 1.75 mm max height |
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SCALE 2.800 |
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SMALL OUTLINE INTEGRATED CIRCUIT |
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C |
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SEATING PLANE |
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.228-.244 TYP |
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[5.80-6.19] |
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.004 [0.1] C |
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A |
PIN 1 ID AREA |
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6X |
.050 |
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8 |
[1.27] |
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1 |
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.189-.197 |
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2X |
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[4.81-5.00] |
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.150 |
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NOTE 3 |
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[3.81] |
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4X (0 -15 ) |
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4 |
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5 |
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8X .012-.020 |
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B |
.150-.157 |
[0.31-0.51] |
.069 MAX |
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[3.81-3.98] |
.010 [0.25] |
C A B |
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[1.75] |
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NOTE 4 |
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.005-.010 |
TYP |
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[0.13-0.25] |
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4X (0 -15 ) |
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SEE DETAIL A |
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.010 |
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[0.25] |
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0 - 8 |
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.004-.010 |
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[0.11-0.25] |
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.016-.050 |
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[0.41-1.27] |
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DETAIL A |
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(.041) |
TYPICAL |
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[1.04] |
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4214825/C |
02/2019 |
NOTES: |
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1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
|
EXAMPLE BOARD LAYOUT |
D0008A |
SOIC - 1.75 mm max height |
|
SMALL OUTLINE INTEGRATED CIRCUIT |
8X (.061 ) |
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[1.55] |
SYMM |
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SEE |
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1 |
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DETAILS |
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8 |
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8X (.024) |
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[0.6] |
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SYMM |
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(R.002 ) TYP |
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5 |
[0.05] |
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4 |
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6X (.050 ) |
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[1.27] |
(.213) |
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[5.4] |
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LAND PATTERN EXAMPLE |
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EXPOSED METAL SHOWN |
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SCALE:8X |
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METAL |
SOLDER MASK |
SOLDER MASK |
METAL UNDER |
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OPENING |
OPENING |
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SOLDER MASK |
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EXPOSED |
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EXPOSED |
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METAL |
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METAL |
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.0028 MAX |
.0028 MIN |
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[0.07] |
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[0.07] |
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ALL AROUND |
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ALL AROUND |
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NON SOLDER MASK |
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SOLDER MASK |
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DEFINED |
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DEFINED |
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SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6.Publication IPC-7351 may have alternate designs.
7.Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
|
EXAMPLE STENCIL DESIGN |
D0008A |
SOIC - 1.75 mm max height |
|
SMALL OUTLINE INTEGRATED CIRCUIT |
8X (.061 |
) |
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|
[1.55] |
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SYMM |
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1 |
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8 |
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8X (.024) |
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[0.6] |
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SYMM |
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(R.002 ) TYP |
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4 |
5 |
[0.05] |
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6X (.050 ) |
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[1.27] |
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(.213) |
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[5.4] |
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SOLDER PASTE EXAMPLE |
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BASED ON .005 INCH [0.125 MM] THICK STENCIL |
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SCALE:8X |
|
4214825/C 02/2019
NOTES: (continued)
8.Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations.
9.Board assembly site may have different recommendations for stencil design.
www.ti.com
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Last updated 10/2025