- •FEATURES
- •APPLICATIONS
- •GENERAL DESCRIPTION
- •FUNCTIONAL BLOCK DIAGRAM
- •PRODUCT HIGHLIGHTS
- •TABLE OF CONTENTS
- •REVISION HISTORY
- •SPECIFICATIONS
- •DC SPECIFICATIONS
- •AC SPECIFICATIONS
- •DIGITAL SPECIFICATIONS
- •SWITCHING SPECIFICATIONS
- •TIMING DIAGRAM
- •ABSOLUTE MAXIMUM RATINGS
- •THERMAL RESISTANCE
- •ESD CAUTION
- •PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
- •EQUIVALENT CIRCUITS
- •TYPICAL PERFORMANCE CHARACTERISTICS
- •THEORY OF OPERATION
- •ANALOG INPUT CONSIDERATIONS
- •Input Common Mode
- •Differential Input Configurations
- •Single-Ended Input Configuration
- •VOLTAGE REFERENCE
- •Internal Reference Connection
- •External Reference Operation
- •CLOCK INPUT CONSIDERATIONS
- •Clock Input Options
- •Clock Duty Cycle
- •JITTER CONSIDERATIONS
- •POWER DISSIPATION AND STANDBY MODE
- •Power-Down Mode
- •Standby Mode
- •DIGITAL OUTPUTS
- •Out-of-Range (OR) Condition
- •Digital Output Enable Function (OEB)
- •TIMING
- •Data Clock Output (DCO)
- •SERIAL PORT INTERFACE (SPI)
- •CONFIGURATION USING THE SPI
- •HARDWARE INTERFACE
- •CONFIGURATION WITHOUT THE SPI
- •MEMORY MAP
- •READING THE MEMORY MAP TABLE
- •Open Locations
- •Default Values
- •Logic Levels
- •SPI-Accessible Features
- •LAYOUT CONSIDERATIONS
- •POWER AND GROUND RECOMMENDATIONS
- •Exposed Paddle Thermal Heat Slug Recommendations
- •RBIAS
- •REFERENCE DECOUPLING
- •EVALUATION BOARD
- •POWER SUPPLIES
- •INPUT SIGNALS
- •OUTPUT SIGNALS
- •DEFAULT OPERATION AND JUMPER SELECTION SETTINGS
- •POWER
- •VREF
- •RBIAS
- •CLOCK
- •PDWN
- •SCLK/DFS
- •SDIO/DCS
- •ALTERNATIVE CLOCK CONFIGURATIONS
- •SCHEMATICS
- •EVALUATION BOARD LAYOUTS
- •BILL OF MATERIALS (BOM)
- •OUTLINE DIMENSIONS
- •ORDERING GUIDE
Single-Ended Input Configuration
Although not recommended, it is possible to operate the AD9233 in a single-ended input configuration, as long as the input voltage swing is within the AVDD supply. Single-ended operation can provide adequate performance in cost-sensitive applications. In this configuration, SFDR and distortion performance degrade due to the large input common-mode swing. If the source impedances on each input are matched, there should be little effect on SNR performance. Figure 41 details a typical single-ended input configuration.
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10µF |
AVDD |
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1kΩ |
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VIN+ |
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0.1µF |
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1V p-p |
49.9Ω |
1kΩ |
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ADC |
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AVDD |
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AD9233 |
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1kΩ |
R |
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VIN– |
05492 |
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10µF |
0.1µF |
1kΩ |
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Figure 41. Single-Ended Input Configuration
VOLTAGE REFERENCE
A stable and accurate voltage reference is built into the AD9233. The input range is adjustable by varying the reference voltage applied to the AD9233, using either the internal reference or an externally applied reference voltage. The input span of the ADC tracks reference voltage changes linearly. The various reference modes are summarized in the following sections. The Reference Decoupling section describes the best practices and requirements for PCB layout of the reference.
Internal Reference Connection
A comparator within the AD9233 detects the potential at the SENSE pin and configures the reference into four possible states, which are summarized in Table 9. If SENSE is grounded, the reference amplifier switch is connected to the internal resistor divider (see Figure 42), setting VREF to 1 V.
Connecting the SENSE pin to VREF switches the reference amplifier output to the SENSE pin, completing the loop and providing a 0.5 V reference output. If a resistor divider is connected external to the chip, as shown in Figure 43, the switch again sets to the SENSE pin.
AD9233
This puts the reference amplifier in a noninverting mode with the VREF output defined as
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VREF 0.5 1 |
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If the SENSE pin is connected to the AVDD pin, the reference amplifier is disabled, and an external reference voltage can be applied to the VREF pin (see the External Reference Operation section).
The input range of the ADC always equals twice the voltage at the reference pin for either an internal or an external reference.
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ADC |
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VIN– |
CORE |
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REFT |
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0.1µF |
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VREF |
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REFB |
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0.1µF |
0.1µF |
SELECT |
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LOGIC |
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SENSE |
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0.5V |
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AD9233 |
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05492 |
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Figure 42. Internal Reference Configuration
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VIN+ |
ADC |
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VIN– |
CORE |
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REFT |
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0.1µF |
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VREF |
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REFB |
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0.1µF |
0.1µF |
R2 |
SELECT |
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SENSE |
LOGIC |
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R1 |
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0.5V |
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AD9233 |
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Figure 43. Programmable Reference Configuration
If the internal reference of the AD9233 is used to drive multiple converters to improve gain matching, the loading of the reference by the other converters must be considered. Figure 44 depicts how the internal reference voltage is affected by loading.
Rev. B | Page 17 of 44
