- •FEATURES
- •APPLICATIONS
- •GENERAL DESCRIPTION
- •FUNCTIONAL BLOCK DIAGRAM
- •PRODUCT HIGHLIGHTS
- •TABLE OF CONTENTS
- •REVISION HISTORY
- •SPECIFICATIONS
- •DC SPECIFICATIONS
- •AC SPECIFICATIONS
- •DIGITAL SPECIFICATIONS
- •SWITCHING SPECIFICATIONS
- •TIMING DIAGRAM
- •ABSOLUTE MAXIMUM RATINGS
- •THERMAL RESISTANCE
- •ESD CAUTION
- •PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
- •EQUIVALENT CIRCUITS
- •TYPICAL PERFORMANCE CHARACTERISTICS
- •THEORY OF OPERATION
- •ANALOG INPUT CONSIDERATIONS
- •Input Common Mode
- •Differential Input Configurations
- •Single-Ended Input Configuration
- •VOLTAGE REFERENCE
- •Internal Reference Connection
- •External Reference Operation
- •CLOCK INPUT CONSIDERATIONS
- •Clock Input Options
- •Clock Duty Cycle
- •JITTER CONSIDERATIONS
- •POWER DISSIPATION AND STANDBY MODE
- •Power-Down Mode
- •Standby Mode
- •DIGITAL OUTPUTS
- •Out-of-Range (OR) Condition
- •Digital Output Enable Function (OEB)
- •TIMING
- •Data Clock Output (DCO)
- •SERIAL PORT INTERFACE (SPI)
- •CONFIGURATION USING THE SPI
- •HARDWARE INTERFACE
- •CONFIGURATION WITHOUT THE SPI
- •MEMORY MAP
- •READING THE MEMORY MAP TABLE
- •Open Locations
- •Default Values
- •Logic Levels
- •SPI-Accessible Features
- •LAYOUT CONSIDERATIONS
- •POWER AND GROUND RECOMMENDATIONS
- •Exposed Paddle Thermal Heat Slug Recommendations
- •RBIAS
- •REFERENCE DECOUPLING
- •EVALUATION BOARD
- •POWER SUPPLIES
- •INPUT SIGNALS
- •OUTPUT SIGNALS
- •DEFAULT OPERATION AND JUMPER SELECTION SETTINGS
- •POWER
- •VREF
- •RBIAS
- •CLOCK
- •PDWN
- •SCLK/DFS
- •SDIO/DCS
- •ALTERNATIVE CLOCK CONFIGURATIONS
- •SCHEMATICS
- •EVALUATION BOARD LAYOUTS
- •BILL OF MATERIALS (BOM)
- •OUTLINE DIMENSIONS
- •ORDERING GUIDE
AD9233
ABSOLUTE MAXIMUM RATINGS
Table 5.
Parameter |
Rating |
ELECTRICAL |
|
AVDD to AGND |
−0.3 V to +2.0 V |
DRVDD to DRGND |
−0.3 V to +3.9 V |
AGND to DRGND |
−0.3 V to +0.3 V |
AVDD to DRVDD |
−3.9 V to +2.0 V |
D0 through D11 to DRGND |
−0.3 V to DRVDD + 0.3 V |
DCO to DRGND |
−0.3 V to DRVDD + 0.3 V |
OR to DRGND |
−0.3 V to DRVDD + 0.3 V |
CLK+ to AGND |
−0.3 V to +3.9 V |
CLK− to AGND |
−0.3 V to +3.9 V |
VIN+ to AGND |
−0.3 V to AVDD + 1.3 V |
VIN− to AGND |
−0.3 V to AVDD + 1.3 V |
VREF to AGND |
−0.3 V to AVDD + 0.2 V |
SENSE to AGND |
−0.3 V to AVDD + 0.2 V |
REFT to AGND |
−0.3 V to AVDD + 0.2 V |
REFB to AGND |
−0.3 V to AVDD + 0.2 V |
SDIO/DCS to DRGND |
−0.3 V to DRVDD + 0.3 V |
PDWN to AGND |
−0.3 V to +3.9 V |
CSB to AGND |
−0.3 V to +3.9 V |
SCLK/DFS to AGND |
−0.3 V to +3.9 V |
OEB to AGND |
−0.3 V to +3.9 V |
|
|
ENVIRONMENTAL |
|
Storage Temperature Range |
–65°C to +125°C |
Operating Temperature Range |
–40°C to +85°C |
Lead Temperature |
300°C |
(Soldering 10 Sec) |
|
Junction Temperature |
150°C |
|
|
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
THERMAL RESISTANCE
The exposed paddle must be soldered to the ground plane for the LFCSP package. Soldering the exposed paddle to the customer board increases the reliability of the solder joints, maximizing the thermal capability of the package.
Table 6.
Package Type |
θJA |
θJC |
Unit |
48-lead LFCSP (CP-48-5) |
26.4 |
2.4 |
°C/W |
|
|
|
|
Typical θJA and θJC are specified for a 4-layer board in still air. Airflow increases heat dissipation, effectively reducing θJA. In addition, metal in direct contact with the package leads from metal traces, and through holes, ground, and power planes, reduces the θJA.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev. B | Page 8 of 44
