- •FEATURES
- •APPLICATIONS
- •GENERAL DESCRIPTION
- •FUNCTIONAL BLOCK DIAGRAM
- •PRODUCT HIGHLIGHTS
- •TABLE OF CONTENTS
- •REVISION HISTORY
- •SPECIFICATIONS
- •DC SPECIFICATIONS
- •AC SPECIFICATIONS
- •DIGITAL SPECIFICATIONS
- •SWITCHING SPECIFICATIONS
- •TIMING DIAGRAM
- •ABSOLUTE MAXIMUM RATINGS
- •THERMAL RESISTANCE
- •ESD CAUTION
- •PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
- •EQUIVALENT CIRCUITS
- •TYPICAL PERFORMANCE CHARACTERISTICS
- •THEORY OF OPERATION
- •ANALOG INPUT CONSIDERATIONS
- •Input Common Mode
- •Differential Input Configurations
- •Single-Ended Input Configuration
- •VOLTAGE REFERENCE
- •Internal Reference Connection
- •External Reference Operation
- •CLOCK INPUT CONSIDERATIONS
- •Clock Input Options
- •Clock Duty Cycle
- •JITTER CONSIDERATIONS
- •POWER DISSIPATION AND STANDBY MODE
- •Power-Down Mode
- •Standby Mode
- •DIGITAL OUTPUTS
- •Out-of-Range (OR) Condition
- •Digital Output Enable Function (OEB)
- •TIMING
- •Data Clock Output (DCO)
- •SERIAL PORT INTERFACE (SPI)
- •CONFIGURATION USING THE SPI
- •HARDWARE INTERFACE
- •CONFIGURATION WITHOUT THE SPI
- •MEMORY MAP
- •READING THE MEMORY MAP TABLE
- •Open Locations
- •Default Values
- •Logic Levels
- •SPI-Accessible Features
- •LAYOUT CONSIDERATIONS
- •POWER AND GROUND RECOMMENDATIONS
- •Exposed Paddle Thermal Heat Slug Recommendations
- •RBIAS
- •REFERENCE DECOUPLING
- •EVALUATION BOARD
- •POWER SUPPLIES
- •INPUT SIGNALS
- •OUTPUT SIGNALS
- •DEFAULT OPERATION AND JUMPER SELECTION SETTINGS
- •POWER
- •VREF
- •RBIAS
- •CLOCK
- •PDWN
- •SCLK/DFS
- •SDIO/DCS
- •ALTERNATIVE CLOCK CONFIGURATIONS
- •SCHEMATICS
- •EVALUATION BOARD LAYOUTS
- •BILL OF MATERIALS (BOM)
- •OUTLINE DIMENSIONS
- •ORDERING GUIDE
AD9233
OUTLINE DIMENSIONS
PIN 1
INDICATOR
AREA
0.80
0.75
0.70
SEATING
PLANE
PKG-005092
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7.10 |
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0.30 |
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7.00 SQ |
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6.90 |
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0.23 |
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0.18 |
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37 |
48 |
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36 |
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1 |
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0.50 |
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BSC |
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EXPOSED |
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PAD |
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DETAIL A (JEDEC 95)
PIN 1 INDICATOR AR EA OP TIONS (SEE DETAIL A)
4.20
4.10 SQ
4.00
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TOP VIEW |
0.45 |
24 |
BOTTOM VIEW |
13 |
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0.20 MIN |
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0.40 |
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0.35
5.50 REF 
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FOR PROPER CONNECTION OF |
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END VIEW |
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0.05 MAX |
THE EXPOSED PAD, REFER TO |
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THE PIN CONFIGURATION AND |
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0.02 NOM |
FUNCTION DESCRIPTIONS |
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COPLANARITY |
SECTION OF THIS DATA SHEET. |
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0.08 |
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0.200 REF |
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-B |
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COMPLIANT TO JEDEC STANDARDS MO-220-WKKD-4 |
10-10-2018 |
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Figure 71. 48-Lead Frame Chip Scale Package [LFCSP] 7 mm × 7 mm Body and 0.75 mm Package Height (CP-48-5)
Dimensions shown in millimeters
ORDERING GUIDE
Model |
Temperature Range |
Package Description |
Package Option1 |
AD9233BCPZ-1252 |
–40°C to +85°C |
48-Lead Lead Frame Chip Scale Package [LFSCP] |
CP-48-5 |
AD9233BCPZRL7–1252 |
–40°C to +85°C |
48-Lead Lead Frame Chip Scale Package [LFSCP] |
CP-48-5 |
AD9233BCPZ-1052 |
–40°C to +85°C |
48-Lead Lead Frame Chip Scale Package [LFSCP] |
CP-48-5 |
AD9233BCPZRL7–1052 |
–40°C to +85°C |
48-Lead Lead Frame Chip Scale Package [LFSCP] |
CP-48-5 |
AD9233BCPZ-802 |
–40°C to +85°C |
48-Lead Lead Frame Chip Scale Package [LFSCP] |
CP-48-5 |
AD9233BCPZRL7–802 |
–40°C to +85°C |
48-Lead Lead Frame Chip Scale Package [LFSCP] |
CP-48-5 |
AD9233-125EB |
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Evaluation Board |
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AD9233-105EB |
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Evaluation Board |
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AD9233-80EB |
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Evaluation Board |
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1 It is required that the exposed paddle be soldered to the AGND plane to achieve the best electrical and thermal performance . 2 Z = Pb-free part.
Rev. B | Page 42 of 44
AD9233
NOTES
Rev. B | Page 43 of 44
AD9233
NOTES
©2006–2020 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners.
D05492-9/20(B)
Rev. B | Page 44 of 44
