PCI_22

Revision 2.2

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4.2.5. Vendor Provided Specification

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4.2.6. Pinout Recommendation

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131

Revision 2.2

PCI Card Edge

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4.3. System (Motherboard) Specification

4.3.1. Clock Skew

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31Non-resistive connections of IDSEL to one of the AD[xx] lines create a technical violation of the single load per expansion board rule. PCI protocol provides for pre-driving of address lines in configuration cycles, and it is recommended that this be done in order to allow a resistive coupling of IDSEL. In absence of this, signal performance must be derated for the extra IDSEL load.

32The system designer must address an additional source of skew. This clock skew occurs between two

components that have clock input trip points at opposite ends of the Vil - Vih range. In certain circumstances, this can add to the clock skew measurement as described here. In all cases, total clock skew

must be limited to the specified number.

132

Revision 2.2

7DEOH &ORFN 6NHZ 3DUDPHWHUV

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33 Component vendors should note that a fixed timing relationship between RST# and power sequencing cannot be guaranteed in all cases.

133

Revision 2.2

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134

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Implementation Note: Trhfa

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34 This reset timing figure optionally shows the "PWR_GOOD" signal as a pulse which is used to time the RST# pulse. In many systems, "PWR_GOOD" may be a level, in which case the RST# pulse must be timed in another way.

135

Revision 2.2

4.3.3. Pull-ups

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136

Revision 2.2

4.3.4.3. Decoupling

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138

Revision 2.2

Implementation Note: Determining the End of Tprop

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