PCI_22

Revision 2.2

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Logic internal to a device must never use the signal received from the bus while that device is driving the bus. If internal logic requires the state of a bus signal while the device is driving the bus, that logic must use the internal signal (the one going to the output buffer of the device) rather than the signal received from the device input buffer. For example, if logic internal to a device continuously monitors the state of FRAME# on the bus, that logic must use the signal from the device input buffer when the device is not the current bus master, and it must use the internally generated FRAME# when the device is the current bus master.

112

Dual Voltage Signaling Board

I/O buffers powered on connector dependent rail

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27 While the primary goal of the PCI 5V to 3.3V transition strategy is to spare vendors the burden and expense of implementing 3.3V parts that are "5V tolerant," such parts are not excluded. If a PCI component of this type is used on the Universal board, its I/O buffers may optionally be connected to the 3.3V rail rather than the "I/O" designated power pins; but high clamp diodes must still be connected to the "I/O" designated power pins. (Refer to the last paragraph of Section 4.2.1.2. - "Clamping directly to the 3.3V rail with a simple diode must never be used in the 5V signaling environment.") Since the effective operation of these high clamp diodes may be critical to both signal quality and device reliability, the designer must provide enough extra "I/O" designated power pins on a component to handle the current spikes associated with the 5V maximum AC waveforms (Section 4.2.1.3.).

114

Revision 2.2

4.1.2. Dynamic vs. Static Drive Specification

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4.2. Component Specification

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28 It may be desirable to perform some production tests at bare silicon pads. Such tests may have different parameters than those specified here and must be correlated back to this specification.

115

Revision 2.2

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116

Revision 2.2

4.2.1. 5V Signaling Environment

4.2.1.1. DC Specifications

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NOTES:

1.Input leakage currents include hi-Z output leakage for all bi-directional buffers with tri-state outputs.

2.Signals without pull-up resistors must have 3 mA low output current. Signals requiring pull up must have 6 mA; the latter include, FRAME#, TRDY#, IRDY#, DEVSEL#, STOP#, SERR#, PERR#, LOCK#, INTA#, INTB#, INTC#, INTD#, and, when used, AD[63::32], C/BE[7::4]#, PAR64, REQ64#, and ACK64#.

3.Absolute maximum pin capacitance for a PCI input is 10 pF (except for CLK) with an exception granted to motherboard-only devices up to 16 pF, in order to accommodate PGA packaging. This means, in general, that components for expansion boards need to use alternatives to ceramic PGA packaging (i.e., PQFP, SGA, etc.).

4.Lower capacitance on this input-only pin allows for non-resistive coupling to AD[xx].

5.This is a recommendation, not an absolute requirement. The actual value should be provided with the component data sheet.

6.This input leakage is the maximum allowable leakage into the PME# open drain driver when power is

removed from Vcc of the component. This assumes that no event has occurred to cause the device to attempt to assert PME#.

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117

Revision 2.2

4.This parameter is to be interpreted as the cumulative edge rate across the specified range, rather than the instantaneous rate at any point within the transition range. The specified load (diagram below) is optional; i.e., the designer may elect to meet this parameter with an unloaded output per revision 2.0 of the PCI Local Bus Specification. However, adherence to both maximum and minimum parameters is required (the maximum is not simply a guideline). Since adherence to the maximum slew rate was not required prior to revision 2.1 of the specification, there may be components in the market for some time that have faster edge rates; therefore, motherboard designers must bear in mind that rise and fall times faster than this specification could occur and should ensure that signal integrity modeling accounts for this. Rise slew rate does not apply to open drain outputs.

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