PCI_22
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Revision 2.2
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Figures |
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Figure 1-1: PCI Local Bus Applications .................................................................................... |
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Figure 1-2: PCI System Block Diagram..................................................................................... |
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Figure 2-1: PCI Pin List ............................................................................................................. |
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Figure 3-1: Address Phase Formats of Configuration Transactions ........................................ |
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Figure 3-2: Layout of CONFIG_ADDRESS Register ............................................................. |
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Figure 3-3: Host Bridge Translation for Type 0 Configuration Transactions |
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Address Phase....................................................................................................... |
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Figure 3-4: Configuration Read ............................................................................................... |
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Figure 3-5: Basic Read Operation ............................................................................................ |
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Figure 3-6: Basic Write Operation ........................................................................................... |
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Figure 3-7: Master Initiated Termination ................................................................................. |
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Figure 3-8: Master-Abort Termination .................................................................................... |
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Figure 3-9: Retry ...................................................................................................................... |
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Figure 3-10: Disconnect With Data.......................................................................................... |
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Figure 3-11: Master Completion Termination ......................................................................... |
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Figure 3-12: Disconnect-1 Without Data Termination ............................................................ |
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Figure 3-13: Disconnect-2 Without Data Termination ............................................................ |
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Figure 3-14: Target-Abort ........................................................................................................ |
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Figure 3-15: Basic Arbitration ................................................................................................. |
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Figure 3-16: Arbitration for Back-to-Back Access .................................................................. |
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Figure 3-17: DEVSEL# Assertion........................................................................................... |
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Figure 3-18: Address Stepping ................................................................................................. |
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Figure 3-19: Interrupt Acknowledge Cycle.............................................................................. |
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Figure 3-20: Parity Operation................................................................................................... |
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Figure 3-21: |
64-bit Read Request With 64-bit Transfer ........................................................ |
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Figure 3-22: |
64-bit Write Request With 32-bit Transfer ....................................................... |
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Figure 3-23. 64-Bit Dual Address Read Cycle....................................................................... |
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Figure 4-1: PCI Board Connectors ......................................................................................... |
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Figure 4-2: V/I Curves for 5V Signaling................................................................................ |
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Figure 4-3: Maximum AC Waveforms for 5V Signaling ...................................................... |
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Figure 4-4: V/I Curves for 3.3V Signaling............................................................................. |
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Figure 4-5: Maximum AC Waveforms for 3.3V Signaling ................................................... |
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Figure 4-6: Clock Waveforms ................................................................................................ |
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Figure 4-7: Output Timing Measurement Conditions ............................................................ |
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Figure 4-8: Input Timing Measurement Conditions .............................................................. |
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Figure 4-9: Suggested Pinout for PQFP PCI Component ...................................................... |
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Figure 4-10: Clock Skew Diagram ......................................................................................... |
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Figure 4-11: Reset Timing...................................................................................................... |
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Figure 4-12: Measurement of Tprop, 5 Volt Signaling.......................................................... |
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Figure 5-1: PCI Raw Card (5V) ............................................................................................. |
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Figure 5-2: PCI Raw Card (3.3V and Universal) ................................................................... |
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Figure 5-3: PCI Raw Variable Height Short Card (5V, 32-bit) ............................................. |
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Figure 5-4: PCI Raw Variable Height Short Card (3.3V, 32-bit) .......................................... |
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Figure 5-5: PCI Raw Variable Height Short Card (5V, 64-bit) ............................................. |
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Figure 5-6: PCI Raw Variable Height Short Card (3.3V, 64-bit) .......................................... |
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Figure 5-7: PCI Card Edge Connector Bevel ......................................................................... |
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Figure 5-8: ISA Assembly (5V) ............................................................................................. |
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Figure 5-9: ISA Assembly (3.3V and Universal) ................................................................... |
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Figure 5-10: MC Assembly (5V) ........................................................................................... |
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Figure 5-11: MC Assembly (3.3V) ........................................................................................ |
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Figure 5-12: ISA Bracket ....................................................................................................... |
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Figure 5-13: ISA Retainer ...................................................................................................... |
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Figure 5-14: I/O Window Height ........................................................................................... |
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Figure 5-15: Adapter Installation With Large I/O Connector ................................................ |
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Figure 5-16: MC Bracket Brace ............................................................................................. |
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Figure 5-17: MC Bracket........................................................................................................ |
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Figure 5-18: MC Bracket Details ........................................................................................... |
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Figure 5-19: |
32-bit Connector ................................................................................................ |
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Figure 5-20: 5V/32-bit Connector Layout Recommendation ................................................ |
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Figure 5-21: 3.3V/32-bit Connector Layout Recommendation ............................................. |
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Figure 5-22: 5V/64-bit Connector .......................................................................................... |
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Figure 5-23: 5V/64-bit Connector Layout Recommendation ................................................ |
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Figure 5-24: 3.3V/64-bit Connector ....................................................................................... |
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Figure 5-25: 3.3V/64-bit Connector Layout Recommendation ............................................. |
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Figure 5-26: 5V/32-bit Card Edge Connector Dimensions and Tolerances .......................... |
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Figure 5-27: 5V/64-bit Card Edge Connector Dimensions and Tolerances .......................... |
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Figure 5-28: 3.3V/32-bit Card Edge Connector Dimensions and Tolerances ....................... |
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Figure 5-29: 3.3V/64-bit Card Edge Connector Dimensions and Tolerances ....................... |
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Figure 5-30: Universal 32-bit Card Edge Connector Dimensions and Tolerances ................ |
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Figure 5-31: Universal 64-bit Card Edge Connector Dimensions and Tolerances ................ |
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Figure 5-32: PCI Card Edge Connector Contacts .................................................................. |
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Figure 5-33: PCI Connector Location on Planar Relative to Datum |
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on the ISA Connector ....................................................................................... |
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Figure 5-34: PCI Connector Location on Planar Relative to Datum |
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on the EISA Connector..................................................................................... |
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Figure 5-35: PCI Connector Location on Planar Relative to Datum |
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on the MC Connector ....................................................................................... |
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Figure 5-36: |
32-bit PCI Riser Connector ............................................................................... |
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Figure 5-37: |
32-bit/5V Riser Connector Footprint ................................................................ |
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Figure 5-38: |
32-bit/3.3V Riser Connector Footprint ............................................................. |
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Figure 5-39: |
64-bit/5V Riser Connector ............................................................................... |
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Figure 5-40: |
64-bit/5V Riser Connector Footprint ................................................................ |
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Figure 5-41: |
64-bit/3.3V Riser Connector ............................................................................ |
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Figure 5-42: |
64-bit/3.3V Riser Connector Footprint.............................................................. |
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Figure 6-1: Type 00h Configuration Space Header ............................................................... |
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Figure 6-2: Command Register Layout .................................................................................. |
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Figure 6-3: Status Register Layout......................................................................................... |
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Figure 6-4: BIST Register Layout .......................................................................................... |
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Figure 6-5: Base Address Register for Memory .................................................................... |
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Figure 6-6: Base Address Register for I/O ............................................................................. |
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Figure 6-7: Expansion ROM Base Address Register Layout................................................. |
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Figure 6-8: PCI Expansion ROM Structure ........................................................................... |
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Figure 6-9: Typical Image Layout.......................................................................................... |
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Figure 6-10: Example Capabilities List.................................................................................. |
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Figure 6-11: Message Signaled Interrupt Capability Structure .............................................. |
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Figure 7-1: 33 MHz PCI vs. 66 MHz PCI Timing ................................................................. |
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Figure 7-2: 3.3V Clock Waveform......................................................................................... |
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Figure 7-3: Output Timing Measurement Conditions ............................................................ |
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Figure 7-4: Input Timing Measurement Conditions .............................................................. |
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Figure 7-5: Tval(max) Rising Edge........................................................................................ |
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Figure 7-6: Tval(max) Falling Edge....................................................................................... |
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Figure 7-7: Tval (min) and Slew Rate .................................................................................... |
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Figure 7-8: Recommended Clock Routing ............................................................................. |
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Figure 7-9: Clock Skew Diagram ........................................................................................... |
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Figure 7-10: Measurement of Tprop ...................................................................................... |
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Figure D-1: Programming Interface Byte Layout for IDE Controller Class Code ................ |
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Figure E-1: Example Producer - Consumer Model ................................................................ |
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Figure E-2: Example System with PCI-to-PCI Bridges ......................................................... |
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Figure F-1: Starting an Exclusive Access .............................................................................. |
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Figure F-2: Continuing an Exclusive Access ......................................................................... |
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Figure F-3: Accessing a Locked Agent .................................................................................. |
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Figure I-1: VPD Capability Structure .................................................................................... |
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Figure I-2: Small Resource Data Type Tag Bit Definitions................................................... |
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Figure I-3: Large Resource Data Type Tag Bit Definitions................................................... |
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Figure I-4: Resource Data Type Flags for a Typical VPD ..................................................... |
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Figure I-5: VPD Format ......................................................................................................... |
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Preface
Specification Supersedes Earlier Documents
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Incorporation of Engineering Change Requests (ECRs)
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ECR
New Capabilities
Sub ID
PME#
MECH ECN# 1
MECH ECN# 2
MECH ECN# 3
MECH ECN# 4
Description
Changes to configuration structure to define additional capabilities of a PCI function
Subsystem vendor configuration space changed from optional to required for most classes of devices
Describes wake-up function and assigns (previously reserved) pin on PCI bus
Bracket mounting for EMI reduction
Increase size of I/O window to enable new connectors
I/O connector volume to enable add-in card insertion
Riser connector-add-in card interface
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ECR
MECH ECN# 5
MECH ECN# 6
Posted Memory
Writes
Tprop
RST# TIMING
VPD (Revised)
3.3 V Aux
Max Retry Time
Msg Interrupt
Spread Spectrum
Clocking
Description
Tighten critical tolerance to improve add-in card seating
Mechanical errata (wrong datum ref), components free areas
Clarified requirements for posted memory writes to prevent situations which may lead to a deadlock
Clarifies measurement and determination of Tprop times for 33/66 MHz
New timing requirements between RST# and the first transaction on the bus and the first access to a device
Provides alternate access method to vital product data
Specifies a standard source of power for power management wake event logic
Devices cannot Retry a memory write request for longer than 10 μs
Method by which an I/O controller can deliver message based interrupt
Adds spread spectrum clocking (SSC) to the specification
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Document Conventions
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asserted, deasserted |
The terms asserted and deasserted refer to the |
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globally visible state of the signal on the clock edge, |
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not to signal transitions. |
edge, clock edge |
The terms edge and clock edge refer to the rising edge |
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of the clock. On the rising edge of the clock is the |
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only time signals have any significance on the PCI |
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bus. |
# |
A # symbol at the end of a signal name indicates that |
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the signal’s asserted state occurs when it is at a low |
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voltage. The absence of a # symbol indicates that the |
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signal is asserted at a high voltage. |
reserved |
The contents or undefined states or information are |
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not defined at this time. Using any reserved area in |
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the PCI specification is not permitted. All areas of |
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the PCI specification can only be changed according |
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to the by-laws of the PCI Special Interest Group. Any |
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use of the reserved areas of the PCI specification will |
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result in a product that is not PCI-compliant. The |
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functionality of any such product cannot be |
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guaranteed in this or any future revision of the PCI |
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specification. |
signal names |
Signal names are indicated with this bold font. |
signal range |
A signal name followed by a range enclosed in |
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brackets, for example AD[31::00], represents a range |
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of logically related signals. The first number in the |
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range indicates the most significant bit (msb) and the |
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last number indicates the least significant bit (lsb). |
implementation notes |
Implementation notes are enclosed in a box. They are |
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not part of the PCI specification and are included for |
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clarification and illustration only. |
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