- •A.1 Notes on Using OPCODE Tables
- •A.2 Key to Abbreviations
- •A.2.1 Codes for Addressing Method
- •A.2.2 Codes for Operand Type
- •A.2.3 Register Codes
- •A.3 Opcode Look-up Examples
- •A.3.1 One-Byte Opcode Instructions
- •A.3.2 Two-Byte Opcode Instructions
- •A.3.3 Opcode Map Notes
- •A.3.4 Opcode Extensions for One-Byte and Two-Byte Opcodes
- •A.3.5 Escape Opcode Instructions
- •A.3.5.1 Escape Opcodes with D8 as First Byte
- •A.3.5.2 Escape Opcodes with D9 as First Byte
- •A.3.5.3 Escape Opcodes with DA as First Byte
- •A.3.5.4 Escape Opcodes with DB as First Byte
- •A.3.5.5 Escape Opcodes with DC as First Byte
- •A.3.5.6 Escape Opcodes with DD as First Byte
- •A.3.5.7 Escape Opcodes with DE as First Byte
- •A.3.5.8 Escape Opcodes with DF As First Byte
- •APPENDIX B Instruction Formats and Encodings
- •B.1 Machine Instruction Format
- •B.1.1 Legacy Prefixes
- •B.1.2 REX Prefixes
- •B.1.3 Opcode Fields
- •B.1.4 Special Fields
- •B.1.4.1 Reg Field (reg) for Non-64-Bit Modes
- •B.1.4.2 Reg Field (reg) for 64-Bit Mode
- •B.1.4.3 Encoding of Operand Size (w) Bit
- •B.1.4.4 Sign-Extend (s) Bit
- •B.1.4.5 Segment Register (sreg) Field
- •B.1.4.6 Special-Purpose Register (eee) Field
- •B.1.4.7 Condition Test (tttn) Field
- •B.1.4.8 Direction (d) Bit
- •B.1.5 Other Notes
- •B.2 General-Purpose Instruction Formats and Encodings for Non-64-Bit Modes
- •B.2.1 General Purpose Instruction Formats and Encodings for 64-Bit Mode
- •B.4 64-bit Mode Instruction Encodings for SIMD Instruction Extensions
- •B.5 MMX Instruction Formats and Encodings
- •B.5.1 Granularity Field (gg)
- •B.5.3 MMX Instruction Formats and Encodings Table
- •B.6 P6 Family INstruction Formats and Encodings
- •B.7 SSE Instruction Formats and Encodings
- •B.8 SSE2 Instruction Formats and Encodings
- •B.8.1 Granularity Field (gg)
- •B.9 SSE3 Formats and Encodings Table
- •B.10 Special Encodings for 64-Bit Mode
- •B.11 Floating-Point Instruction Formats and Encodings
- •C.1 Simple Intrinsics
- •INDEX FOR VOLUME 2A & 2B
- •INTEL SALES OFFICES
OPCODE MAP
A.3.4 Opcode Extensions for One-Byte and Two-Byte Opcodes
Some 1-byte and 2-byte opcodes use bits 3-5 of the ModR/M byte (nnn field in Figure A-1) as an extension of the opcode. The bits 3-5 also correspond to the “/digit” portion of opcode notation.
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mod |
nnn |
r/m |
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Figure A-1. ModR/M Byte nnn Field (Bits 5, 4, and 3)
Opcodes that have opcode extensions are indicated in Table A-6 and organized by group number. Group numbers (from 1 to 16, second column) provide a table entry point. The encoding for the r/m field for each instruction can be established using the third column of the table.
For example: an ADD instruction with a 1-byte opcode of 80H is a Group 1 instruction. Table A-6 indicates that the opcode extension field encoded in the ModR/M byte for this instruction is 000B. The r/m field can be encoded to access a register (11B) or a memory address using a specified addressing mode (for example: mem = 00B, 01B, 10B).
Table A-6. Non-64-bit Mode Opcode Extensions for One-byte and
Two-byte Opcodes by Group Number†
Opcode |
Group |
Mod 7,6 |
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Encoding of Bits [5:3] of the ModR/M Byte |
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000 |
001 |
010 |
011 |
100 |
101 |
110 |
111 |
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80-83 |
1 |
mem,11B |
ADD |
OR |
ADC |
SBB |
AND |
SUB |
XOR |
CMP |
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C0, C1 reg, |
2 |
mem,11B |
ROL |
ROR |
RCL |
RCR |
SHL/SAL |
SHR |
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SAR |
imm |
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D0, D1 |
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reg, 1 |
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D2, D3 reg, |
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CL |
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F6, F7 |
3 |
mem,11B |
TEST |
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NOT |
NEG |
MUL |
IMUL |
DIV |
IDIV |
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Ib/Iv |
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AL/eAX |
AL/eAX |
AL/eAX |
AL/eAX |
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FE |
4 |
mem,11B |
INC |
DEC |
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Eb |
Eb |
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FF |
5 |
mem,11B |
INC |
DEC |
CALLN |
CALLF |
JMPN |
JMPF |
PUSH |
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Ev |
Ev |
Ev |
Ep 1J |
Ev |
Ep1J |
Ev |
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0F 00 |
6 |
mem,11B |
SLDT |
STR |
LLDT |
LTR |
VERR |
VERW |
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Ew |
Ev |
Ew |
Ew |
Ew |
Ew |
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0F 01 |
7 |
mem,11B |
SGDT |
SIDT |
LGDT |
LIDT |
SMSW |
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LMSW |
INVLPG |
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Ms |
Ms |
Ms |
Ms |
Ew |
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Ew |
Mb |
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MONITOR |
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eAX, eCX, |
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eDX |
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(000)1E |
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MWAIT |
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eAX, eCX |
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(001)1E |
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A-18 Vol. 2B
OPCODE MAP
Table A-6. Non-64-bit Mode Opcode Extensions for One-byte and
Two-byte Opcodes by Group Number† (Contd.)
Opcode |
Group |
Mod 7,6 |
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Encoding of Bits 5,4,3 of the ModR/M Byte |
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000 |
001 |
010 |
011 |
100 |
101 |
110 |
111 |
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0F BA |
8 |
mem,11B |
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BT |
BTS |
BTR |
BTC |
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0F C7 |
9 |
mem,11B |
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CMPXCH8B |
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Mq |
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0F B9 |
10 |
mem,11B |
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C6 |
11 |
mem,11B |
MOV |
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Eb, Ib |
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C7 |
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MOV |
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Ev, Iv |
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0F 71 |
12 |
mem,11B |
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PSRLW |
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PSRAW |
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PSLLW |
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Pq, Ib |
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Pq, Ib |
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Pq, Ib |
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PSRLW |
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PSRAW |
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PSLLW |
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(66) |
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(66) |
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(66) |
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Pdq, Ib |
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Pdq, Ib |
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Pdq, Ib |
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0F 72 |
13 |
mem,11B |
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PSRLD |
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PSRAD |
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PSLLD |
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Pq, Ib |
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Pq, Ib |
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Pq, Ib |
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PSRLD |
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PSRAD |
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PSLLD |
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(66) |
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(66) |
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(66) |
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Wdq, Ib |
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Wdq, Ib |
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Wdq, Ib |
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0F 73 |
14 |
mem,11B |
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PSRLQ |
PSRLDQ |
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PSLLQ |
PSLLDQ |
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Pq, Ib |
(66) |
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Pq, Ib |
(66) |
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PSRLQ |
Wdq, Ib |
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PSLLQ |
Wdq, Ib |
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(66) |
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(66) |
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Wdq, Ib |
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Wdq, Ib |
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0F AE |
15 |
mem,11B |
FXSAVE |
FXRSTOR |
LDMXCSR |
STMXCSR |
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CLFLUSH |
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LFENCE |
MFENCE |
SFENCE |
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(000) 1E |
(000) 1E |
(000) 1E |
0F 18 |
16 |
mem,11B |
PREFETCH - |
PREFETCH- |
PREFETCH- |
PREFETCH- |
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NTA |
T0 |
T1 |
T2 |
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NOTES:
†All blanks in all opcode maps are reserved and must not be used. Do not depend on the operation of undefined or reserved opcodes.
Vol. 2B A-19
OPCODE MAP
Table A-7. 64-bit Mode Opcode Extensions for One-Byte and
Two-byte Opcodes by Group Number†
Opcode |
Group |
Mod 7,6 |
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Encoding of Bits 5,4,3 of the ModR/M Byte |
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000 |
001 |
010 |
011 |
100 |
101 |
110 |
111 |
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80-83 |
1 |
mem,11B |
ADD |
OR |
ADC |
SBB |
AND |
SUB |
XOR |
CMP |
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C0 reg, imm |
2 |
mem,11B |
ROL1M |
ROR1M |
RCL1M |
RCR1M |
SHL/ |
SHR1M |
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SAR1M |
D0, reg, 1 |
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SAL1M |
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D2 reg, CL |
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C1 reg, imm |
2 |
mem,11B |
ROL |
ROR |
RCL |
RCR |
SHL/ |
SHR |
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SAR |
D1 reg, 1 |
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SAL |
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D3 reg, CL |
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F6, F7 |
3 |
mem,11B |
TEST |
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NOT |
NEG |
MUL |
IMUL |
DIV |
IDIV |
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AL/eAX/ |
AL/eAX/ |
AL/eAX/ |
AL/eAX/ |
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RAX |
RAX |
RAX |
RAX |
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FE |
4 |
mem,11B |
INC |
DEC |
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Eb1M |
Eb1M |
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FF |
5 |
mem,11B |
INC |
DEC |
CALLN1N |
CALLF1J |
JMPN1N |
JMPF1J |
PUSH |
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Ev |
Ev |
Eq |
Ep |
Eq |
Ep |
Ew |
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Eqp |
Eqp |
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Et |
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Et |
Eq |
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0F 00 |
6 |
mem,11B |
SLDT |
STR |
LLDT |
LTR |
VERR |
VERW |
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Ew |
Ev |
Ew |
Ew |
Ew |
Ew |
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0F 01 |
7 |
mem,11B |
SGDT |
SIDT |
LGDT |
LIDT |
SMSW |
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LMSW |
INVLPG |
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Ms |
Ms |
Ms |
Ms |
Ew |
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Ew |
Mb |
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MONITOR |
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SWAPGS |
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RAX, eCX, |
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(000) 1E |
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eDX |
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(000)1E |
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MWAIT |
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eAX, eCX |
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(001)1E |
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0F BA |
8 |
mem,11B |
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BT |
BTS |
BTR |
BTC |
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0F C7 |
9 |
mem,11B |
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CMPXCH8 |
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B Mq |
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CMPXCH1 |
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6B Mdq |
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0F B9 |
10 |
mem,11B |
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C6 |
11 |
mem,11B |
MOV1M |
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Eb, Ib |
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C7 |
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mem,11B |
MOV |
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Ev, Iv |
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Eqp, Ids |
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A-20 Vol. 2B
OPCODE MAP
Table A-7. 64-bit Mode Opcode Extensions for One-Byte and
Two-byte Opcodes by Group Number† (Contd.)
Opcode |
Group |
Mod 7,6 |
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Encoding of Bits 5,4,3 of the ModR/M Byte |
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000 |
001 |
010 |
011 |
100 |
101 |
110 |
111 |
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0F 71 |
12 |
mem,11B |
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PSRLW |
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PSRAW |
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PSLLW |
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Pq, Ib |
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Pq, Ib |
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Pq, Ib |
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PSRLW |
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PSRAW |
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PSLLW |
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(66) |
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(66) |
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(66) |
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Pdq, Ib |
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Pdq, Ib |
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Pdq, Ib |
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0F 72 |
13 |
mem,11B |
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PSRLD |
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PSRAD |
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PSLLD |
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Pq, Ib |
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Pq, Ib |
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Pq, Ib |
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PSRLD |
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PSRAD |
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PSLLD |
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(66) |
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(66) |
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(66) |
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Wdq, Ib |
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Wdq, Ib |
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Wdq, Ib |
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0F 73 |
14 |
mem,11B |
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PSRLQ |
PSRLDQ |
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PSLLQ |
PSLLDQ |
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Pq, Ib |
(66) |
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Pq, Ib |
(66) |
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PSRLQ |
Wdq, Ib |
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PSLLQ |
Wdq, Ib |
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(66) |
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(66) |
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Wdq, Ib |
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Wdq, Ib |
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0F AE |
15 |
mem,11B |
FXSAVE |
FXRSTOR |
LDMXCSR |
STMXCSR |
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CLFLUSH |
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LFENCE |
MFENCE |
SFENCE |
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(000) 1E |
(000) 1E |
(000) 1E |
0F 18 |
16 |
mem,11B |
PREFETCH- |
PREFETCH- |
PREFETCH- |
PREFETCH- |
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NTA |
T0 |
T1 |
T2 |
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NOTES:
†All blanks in the opcode map are reserved and must not be used. Do not depend on the operation of undefined or reserved opcodes.
Vol. 2B A-21