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Figure 1-2. Syntax for CPUID, CR, and MSR Data Presentation

1.4RELATED LITERATURE

Literature related to Intel 64 and IA-32 processors is listed on-line at: http://developer.intel.com/products/processor/index.htm

Some of the documents listed at this web site can be viewed on-line; others can be ordered. The literature available is listed by Intel processor and then by the following literature types: applications notes, data sheets, manuals, papers, and specification updates.

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ABOUT THIS MANUAL

See also:

•The data sheet for a particular Intel 64 or IA-32 processor

•The specification update for a particular Intel 64 or IA-32 processor

•Intel® C++ Compiler documentation and online help http://www3.intel.com/cd/software/products/asmo-na/eng/index.htm

•Intel® Fortran Compiler documentation and online help http://www3.intel.com/cd/software/products/asmo-na/eng/index.htm

•Intel® VTune™ Performance Analyzer documentation and online help http://www3.intel.com/cd/software/products/asmo-na/eng/index.htm

•Intel® 64 and IA-32 Architectures Software Developer’s Manual (in five volumes) http://developer.intel.com/products/processor/manuals/index.htm

•Intel® 64 and IA-32 Architectures Optimization Reference Manual http://developer.intel.com/products/processor/manuals/index.htm

•Intel® Processor Identification with the CPUID Instruction, AP-485 http://www.intel.com/support/processors/sb/cs-009861.htm

•Developing Multi-threaded Applications: A Platform Consistent Approach http://cache-www.intel.com/cd/00/00/05/15/51534_developing_multithreaded _applications.pdf

•Using Spin-Loops on Intel Pentium 4 Processor and Intel Xeon Processor MP http://www3.intel.com/cd/ids/developer/asmona/eng/dc/threading/knowledgebase/19083.htm

More relevant links are:

•Software network link: http://softwarecommunity.intel.com/isn/home/

•Developer centers: http://www3.intel.com/cd/ids/developer/asmo-na/eng/dc/index.htm

•Processor support general link: http://www.intel.com/support/processors/

•Software products and packages: http://www3.intel.com/cd/software/products/asmo-na/eng/index.htm

•Hyper-Threading Technology (HT Technology): http://developer.intel.com/technology/hyperthread/

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CHAPTER 2

INSTRUCTION FORMAT

This chapter describes the instruction format for all Intel 64 and IA-32 processors. The instruction format for protected mode, real-address mode and virtual-8086 mode is described in Section 2.1. Increments provided for IA-32e mode and its submodes are described in Section 2.2.

2.1INSTRUCTION FORMAT FOR PROTECTED MODE, REAL-ADDRESS MODE, AND VIRTUAL-8086 MODE

The Intel 64 and IA-32 architectures instruction encodings are subsets of the format shown in Figure 2-1. Instructions consist of optional instruction prefixes (in any order), primary opcode bytes (up to three bytes), an addressing-form specifier (if required) consisting of the ModR/M byte and sometimes the SIB (Scale-Index-Base) byte, a displacement (if required), and an immediate data field (if required).

Figure 2-1. Intel 64 and IA-32 Architectures Instruction Format

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INSTRUCTION FORMAT

2.1.1Instruction Prefixes

Instruction prefixes are divided into four groups, each with a set of allowable prefix codes. For each instruction, one prefix may be used from each of four groups (Groups 1, 2, 3, 4) and be placed in any order.

•Group 1

—Lock and repeat prefixes:

•F0H—LOCK

•F2H—REPNE/REPNZ (used only with string instructions; when used with the escape opcode 0FH, this prefix is treated as a mandatory prefix for some SIMD instructions)

•F3H—REP or REPE/REPZ (used only with string instructions; when used with the escape opcode 0FH, this prefix is treated as an mandatory prefix for some SIMD instructions)

•Group 2

—Segment override prefixes:

•2EH—CS segment override (use with any branch instruction is reserved)

•36H—SS segment override prefix (use with any branch instruction is reserved)

•3EH—DS segment override prefix (use with any branch instruction is reserved)

•26H—ES segment override prefix (use with any branch instruction is reserved)

•64H—FS segment override prefix (use with any branch instruction is reserved)

•65H—GS segment override prefix (use with any branch instruction is reserved)

—Branch hints:

•2EH—Branch not taken (used only with Jcc instructions)

•3EH—Branch taken (used only with Jcc instructions)

•Group 3

•66H—Operand-size override prefix (when used with the escape opcode 0FH, this is treated as a mandatory prefix for some SIMD instructions)

•Group 4

•67H—Address-size override prefix

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