
- •5.1 Overview
- •5.2 Conventions
- •5.3 VMX Instructions
- •A.1 Using Opcode Tables
- •A.2 Key to Abbreviations
- •A.2.1 Codes for Addressing Method
- •A.2.2 Codes for Operand Type
- •A.2.3 Register Codes
- •A.2.4 Opcode Look-up Examples for One, Two, and Three-Byte Opcodes
- •A.2.4.1 One-Byte Opcode Instructions
- •A.2.4.2 Two-Byte Opcode Instructions
- •A.2.4.3 Three-Byte Opcode Instructions
- •A.2.5 Superscripts Utilized in Opcode Tables
- •A.3 One, Two, and THREE-Byte Opcode Maps
- •A.4 Opcode Extensions For One-Byte And Two-byte Opcodes
- •A.4.1 Opcode Look-up Examples Using Opcode Extensions
- •A.4.2 Opcode Extension Tables
- •A.5 Escape Opcode Instructions
- •A.5.1 Opcode Look-up Examples for Escape Instruction Opcodes
- •A.5.2 Escape Opcode Instruction Tables
- •A.5.2.1 Escape Opcodes with D8 as First Byte
- •A.5.2.2 Escape Opcodes with D9 as First Byte
- •A.5.2.3 Escape Opcodes with DA as First Byte
- •A.5.2.4 Escape Opcodes with DB as First Byte
- •A.5.2.5 Escape Opcodes with DC as First Byte
- •A.5.2.6 Escape Opcodes with DD as First Byte
- •A.5.2.7 Escape Opcodes with DE as First Byte
- •A.5.2.8 Escape Opcodes with DF As First Byte
- •Appendix B Instruction Formats and Encodings
- •B.1 Machine Instruction Format
- •B.1.1 Legacy Prefixes
- •B.1.2 REX Prefixes
- •B.1.3 Opcode Fields
- •B.1.4 Special Fields
- •B.1.4.1 Reg Field (reg) for Non-64-Bit Modes
- •B.1.4.2 Reg Field (reg) for 64-Bit Mode
- •B.1.4.3 Encoding of Operand Size (w) Bit
- •B.1.4.4 Sign-Extend (s) Bit
- •B.1.4.5 Segment Register (sreg) Field
- •B.1.4.6 Special-Purpose Register (eee) Field
- •B.1.4.7 Condition Test (tttn) Field
- •B.1.4.8 Direction (d) Bit
- •B.1.5 Other Notes
- •B.2 General-Purpose Instruction Formats and Encodings for Non-64-Bit Modes
- •B.2.1 General Purpose Instruction Formats and Encodings for 64-Bit Mode
- •B.3 Pentium® Processor Family Instruction Formats and Encodings
- •B.4 64-bit Mode Instruction Encodings for SIMD Instruction Extensions
- •B.5 MMX Instruction Formats and Encodings
- •B.5.1 Granularity Field (gg)
- •B.5.2 MMX Technology and General-Purpose Register Fields (mmxreg and reg)
- •B.5.3 MMX Instruction Formats and Encodings Table
- •B.6 P6 Family INstruction Formats and Encodings
- •B.7 SSE Instruction Formats and Encodings
- •B.8 SSE2 Instruction Formats and Encodings
- •B.8.1 Granularity Field (gg)
- •B.9 SSE3 Formats and Encodings Table
- •B.10 SSSE3 Formats and Encoding Table
- •B.11 Special Encodings for 64-Bit Mode
- •B.12 Floating-Point Instruction Formats and Encodings
- •B.13 VMX Instructions
- •Appendix C InteL® C/C++ Compiler Intrinsics and Functional Equivalents
- •C.1 Simple Intrinsics
- •Intel Sales Offices
- •Index for Volumes 2A & 2B

APPENDIX A
OPCODE MAP
Use the opcode tables in this chapter to interpret Intel 64 and IA-32 architecture object code. Instructions are divided into encoding groups:
•1-byte, 2-byte and 3-byte opcode encodings are used to encode integer, system, MMX technology, SSE/SSE2/SSE3/SSSE3, and VMX instructions. Maps for these instructions are given in Table A-2 through Table A-6.
•Escape opcodes (in the format: ESC character, opcode, ModR/M byte) are used for floating-point instructions. The maps for these instructions are provided in Table A-7 through Table A-22.
NOTE
All blanks in opcode maps are reserved and must not be used. Do not depend on the operation of undefined or blank opcodes.
A.1 USING OPCODE TABLES
Tables in this appendix list opcodes of instructions (including required instruction prefixes, opcode extensions in associated ModR/M byte). Blank cells in the tables indicate opcodes that are reserved or undefined.
The opcode map tables are organized by hex values of the upper and lower 4 bits of an opcode byte. For 1-byte encodings (Table A-2), use the four high-order bits of an opcode to index a row of the opcode table; use the four low-order bits to index a column of the table. For 2-byte opcodes beginning with 0FH (Table A-3), skip any instruction prefixes, the 0FH byte (0FH may be preceded by 66H, F2H, or F3H) and use the upper and lower 4-bit values of the next opcode byte to index table rows and columns. Similarly, for 3-byte opcodes beginning with 0F38H or 0F3AH (Table A-4), skip any instruction prefixes, 0F38H or 0F3AH and use the upper and lower 4-bit values of the third opcode byte to index table rows and columns. See Section A.2.4, “Opcode Look-up Examples for One, Two, and Three-Byte Opcodes.”
When a ModR/M byte provides opcode extensions, this information qualifies opcode execution. For information on how an opcode extension in the ModR/M byte modifies the opcode map in Table A-2 and Table A-3, see Section A.4.
The escape (ESC) opcode tables for floating point instructions identify the eight high order bits of opcodes at the top of each page. See Section A.5. If the accompanying ModR/M byte is in the range of 00H-BFH, bits 3-5 (the top row of the third table on each page) along with the reg bits of ModR/M determine the opcode. ModR/M bytes outside the range of 00H-BFH are mapped by the bottom two tables on each page of the section.
Vol. 2B A-1