- •5.1 Overview
- •5.2 Conventions
- •5.3 VMX Instructions
- •A.1 Using Opcode Tables
- •A.2 Key to Abbreviations
- •A.2.1 Codes for Addressing Method
- •A.2.2 Codes for Operand Type
- •A.2.3 Register Codes
- •A.2.4 Opcode Look-up Examples for One, Two, and Three-Byte Opcodes
- •A.2.4.1 One-Byte Opcode Instructions
- •A.2.4.2 Two-Byte Opcode Instructions
- •A.2.4.3 Three-Byte Opcode Instructions
- •A.2.5 Superscripts Utilized in Opcode Tables
- •A.3 One, Two, and THREE-Byte Opcode Maps
- •A.4 Opcode Extensions For One-Byte And Two-byte Opcodes
- •A.4.1 Opcode Look-up Examples Using Opcode Extensions
- •A.4.2 Opcode Extension Tables
- •A.5 Escape Opcode Instructions
- •A.5.1 Opcode Look-up Examples for Escape Instruction Opcodes
- •A.5.2 Escape Opcode Instruction Tables
- •A.5.2.1 Escape Opcodes with D8 as First Byte
- •A.5.2.2 Escape Opcodes with D9 as First Byte
- •A.5.2.3 Escape Opcodes with DA as First Byte
- •A.5.2.4 Escape Opcodes with DB as First Byte
- •A.5.2.5 Escape Opcodes with DC as First Byte
- •A.5.2.6 Escape Opcodes with DD as First Byte
- •A.5.2.7 Escape Opcodes with DE as First Byte
- •A.5.2.8 Escape Opcodes with DF As First Byte
- •Appendix B Instruction Formats and Encodings
- •B.1 Machine Instruction Format
- •B.1.1 Legacy Prefixes
- •B.1.2 REX Prefixes
- •B.1.3 Opcode Fields
- •B.1.4 Special Fields
- •B.1.4.1 Reg Field (reg) for Non-64-Bit Modes
- •B.1.4.2 Reg Field (reg) for 64-Bit Mode
- •B.1.4.3 Encoding of Operand Size (w) Bit
- •B.1.4.4 Sign-Extend (s) Bit
- •B.1.4.5 Segment Register (sreg) Field
- •B.1.4.6 Special-Purpose Register (eee) Field
- •B.1.4.7 Condition Test (tttn) Field
- •B.1.4.8 Direction (d) Bit
- •B.1.5 Other Notes
- •B.2 General-Purpose Instruction Formats and Encodings for Non-64-Bit Modes
- •B.2.1 General Purpose Instruction Formats and Encodings for 64-Bit Mode
- •B.3 Pentium® Processor Family Instruction Formats and Encodings
- •B.4 64-bit Mode Instruction Encodings for SIMD Instruction Extensions
- •B.5 MMX Instruction Formats and Encodings
- •B.5.1 Granularity Field (gg)
- •B.5.2 MMX Technology and General-Purpose Register Fields (mmxreg and reg)
- •B.5.3 MMX Instruction Formats and Encodings Table
- •B.6 P6 Family INstruction Formats and Encodings
- •B.7 SSE Instruction Formats and Encodings
- •B.8 SSE2 Instruction Formats and Encodings
- •B.8.1 Granularity Field (gg)
- •B.9 SSE3 Formats and Encodings Table
- •B.10 SSSE3 Formats and Encoding Table
- •B.11 Special Encodings for 64-Bit Mode
- •B.12 Floating-Point Instruction Formats and Encodings
- •B.13 VMX Instructions
- •Appendix C InteL® C/C++ Compiler Intrinsics and Functional Equivalents
- •C.1 Simple Intrinsics
- •Intel Sales Offices
- •Index for Volumes 2A & 2B
INSTRUCTION FORMATS AND ENCODINGS
B.9 SSE3 FORMATS AND ENCODINGS TABLE
The tables in this section provide SSE3 formats and encodings. Some SSE3 instructions require a mandatory prefix (66H, F2H, F3H) as part of the two-byte opcode. These prefixes are included in the tables.
When in IA-32e mode, use of the REX.R prefix permits instructions that use general purpose and XMM registers to access additional registers. Some instructions require the REX.W prefix to promote the instruction to 64-bit operation. Instructions that require the REX.W prefix are listed (with their opcodes) in Section B.11.
Table B-28. Formats and Encodings of SSE3 Floating-Point Instructions
Instruction and Format |
Encoding |
|
|
ADDSUBPD—Add /Sub packed DP FP |
|
numbers from XMM2/Mem to XMM1 |
|
|
|
xmmreg2 to xmmreg1 |
01100110:00001111:11010000:11 xmmreg1 |
|
xmmreg2 |
|
|
mem to xmmreg |
01100110:00001111:11010000: mod xmmreg |
|
r/m |
|
|
ADDSUBPS—Add /Sub packed SP FP |
|
numbers from XMM2/Mem to XMM1 |
|
|
|
xmmreg2 to xmmreg1 |
11110010:00001111:11010000:11 xmmreg1 |
|
xmmreg2 |
|
|
mem to xmmreg |
11110010:00001111:11010000: mod xmmreg |
|
r/m |
|
|
HADDPD—Add horizontally packed DP FP |
|
numbers XMM2/Mem to XMM1 |
|
|
|
xmmreg2 to xmmreg1 |
01100110:00001111:01111100:11 xmmreg1 |
|
xmmreg2 |
|
|
mem to xmmreg |
01100110:00001111:01111100: mod xmmreg |
|
r/m |
|
|
HADDPS—Add horizontally packed SP FP |
|
numbers XMM2/Mem to XMM1 |
|
|
|
xmmreg2 to xmmreg1 |
11110010:00001111:01111100:11 xmmreg1 |
|
xmmreg2 |
|
|
mem to xmmreg |
11110010:00001111:01111100: mod xmmreg |
|
r/m |
|
|
HSUBPD—Sub horizontally packed DP FP |
|
numbers XMM2/Mem to XMM1 |
|
|
|
xmmreg2 to xmmreg1 |
01100110:00001111:01111101:11 xmmreg1 |
|
xmmreg2 |
|
|
B-86 Vol. 2B
INSTRUCTION FORMATS AND ENCODINGS
Table B-28. Formats and Encodings of SSE3 Floating-Point Instructions (Contd.)
Instruction and Format |
Encoding |
|
|
mem to xmmreg |
01100110:00001111:01111101: mod xmmreg |
|
r/m |
|
|
HSUBPS—Sub horizontally packed SP FP |
|
numbers XMM2/Mem to XMM1 |
|
|
|
xmmreg2 to xmmreg1 |
11110010:00001111:01111101:11 xmmreg1 |
|
xmmreg2 |
|
|
mem to xmmreg |
11110010:00001111:01111101: mod xmmreg |
|
r/m |
|
|
Table B-29. Formats and Encodings for SSE3 Event Management Instructions
Instruction and Format |
Encoding |
|
|
MONITOR—Set up a linear address range to |
|
be monitored by hardware |
|
|
|
eax, ecx, edx |
0000 1111 : 0000 0001:11 001 000 |
|
|
MWAIT—Wait until write-back store |
|
performed within the range specified by |
|
the instruction MONITOR |
|
|
|
eax, ecx |
0000 1111 : 0000 0001:11 001 001 |
|
|
Table B-30. Formats and Encodings for SSE3 Integer and Move Instructions
Instruction and Format |
Encoding |
|
|
FISTTP—Store ST in int16 (chop) and pop |
|
|
|
m16int |
11011 111 : modA 001 r/m |
FISTTP—Store ST in int32 (chop) and pop |
|
|
|
m32int |
11011 011 : modA 001 r/m |
FISTTP—Store ST in int64 (chop) and pop |
|
|
|
m64int |
11011 101 : modA 001 r/m |
LDDQU—Load unaligned integer 128-bit |
|
|
|
xmm, m128 |
11110010:00001111:11110000: modA xmmreg |
|
r/m |
|
|
MOVDDUP—Move 64 bits representing one |
|
DP data from XMM2/Mem to XMM1 and |
|
duplicate |
|
|
|
xmmreg2 to xmmreg1 |
11110010:00001111:00010010:11 xmmreg1 |
|
xmmreg2 |
|
|
Vol. 2B B-87
INSTRUCTION FORMATS AND ENCODINGS
Table B-30. Formats and Encodings for SSE3 Integer and Move Instructions (Contd.)
Instruction and Format |
Encoding |
|
|
mem to xmmreg |
11110010:00001111:00010010: mod xmmreg |
|
r/m |
|
|
MOVSHDUP—Move 128 bits representing 4 |
|
SP data from XMM2/Mem to XMM1 and |
|
duplicate high |
|
|
|
xmmreg2 to xmmreg1 |
11110011:00001111:00010110:11 xmmreg1 |
|
xmmreg2 |
|
|
mem to xmmreg |
11110011:00001111:00010110: mod xmmreg |
|
r/m |
|
|
MOVSLDUP—Move 128 bits representing 4 |
|
SP data from XMM2/Mem to XMM1 and |
|
duplicate low |
|
|
|
xmmreg2 to xmmreg1 |
11110011:00001111:00010010:11 xmmreg1 |
|
xmmreg2 |
|
|
mem to xmmreg |
11110011:00001111:00010010: mod xmmreg |
|
r/m |
|
|
B.10 SSSE3 FORMATS AND ENCODING TABLE
The tables in this section provide SSSE3 formats and encodings. Some SSSE3 instructions require a mandatory prefix (66H) as part of the three-byte opcode. These prefixes are included in the table below.
Table B-31. Formats and Encodings for SSSE3 Instructions
Instruction and Format |
|
Encoding |
|
|
|
PABSB—Packed Absolute |
|
|
Value Bytes |
|
|
|
|
|
mmreg to mmreg |
0000 |
1111:0011 1000: 0001 1100:11 mmreg1 mmreg2 |
|
|
|
mem to mmreg |
0000 |
1111:0011 1000: 0001 1100: mod mmreg r/m |
|
|
|
xmmreg to xmmreg |
0110 |
0110:0000 1111:0011 1000: 0001 1100:11 xmmreg1 |
|
xmmreg2 |
|
|
|
|
mem to xmmreg |
0110 |
0110:0000 1111:0011 1000: 0001 1100: mod xmmreg r/m |
|
|
|
PABSD—Packed Absolute |
|
|
Value Double Words |
|
|
|
|
|
mmreg to mmreg |
0000 |
1111:0011 1000: 0001 1110:11 mmreg1 mmreg2 |
|
|
|
mem to mmreg |
0000 |
1111:0011 1000: 0001 1110: mod mmreg r/m |
|
|
|
B-88 Vol. 2B
|
|
INSTRUCTION FORMATS AND ENCODINGS |
Table B-31. Formats and Encodings for SSSE3 Instructions (Contd.) |
||
|
|
|
Instruction and Format |
|
Encoding |
|
|
|
xmmreg to xmmreg |
0110 |
0110:0000 1111:0011 1000: 0001 1110:11 xmmreg1 |
|
xmmreg2 |
|
|
|
|
mem to xmmreg |
0110 |
0110:0000 1111:0011 1000: 0001 1110: mod xmmreg r/m |
|
|
|
PABSW—Packed |
|
|
Absolute Value Words |
|
|
|
|
|
mmreg to mmreg |
0000 |
1111:0011 1000: 0001 1101:11 mmreg1 mmreg2 |
|
|
|
mem to mmreg |
0000 |
1111:0011 1000: 0001 1101: mod mmreg r/m |
|
|
|
xmmreg to xmmreg |
0110 |
0110:0000 1111:0011 1000: 0001 1101:11 xmmreg1 |
|
xmmreg2 |
|
|
|
|
mem to xmmreg |
0110 |
0110:0000 1111:0011 1000: 0001 1101: mod xmmreg r/m |
|
|
|
PALIGNR—Packed Align |
|
|
Right |
|
|
|
|
|
mmreg to mmreg |
0000 |
1111:0011 1010: 0000 1111:11 mmreg1 mmreg2 |
|
|
|
mem to mmreg |
0000 |
1111:0011 1010: 0000 1111: mod mmreg r/m |
|
|
|
xmmreg to xmmreg |
0110 |
0110:0000 1111:0011 1010: 0000 1111:11 xmmreg1 |
|
xmmreg2 |
|
|
|
|
mem to xmmreg |
0110 |
0110:0000 1111:0011 1010: 0000 1111: mod xmmreg r/m |
|
|
|
PHADDD—Packed |
|
|
Horizontal Add Double |
|
|
Words |
|
|
|
|
|
mmreg to mmreg |
0000 |
1111:0011 1000: 0000 0010:11 mmreg1 mmreg2 |
|
|
|
mem to mmreg |
0000 |
1111:0011 1000: 0000 0010: mod mmreg r/m |
|
|
|
xmmreg to xmmreg |
0110 |
0110:0000 1111:0011 1000: 0000 0010:11 xmmreg1 |
|
xmmreg2 |
|
|
|
|
mem to xmmreg |
0110 |
0110:0000 1111:0011 1000: 0000 0010: mod xmmreg r/m |
|
|
|
PHADDSW—Packed |
|
|
Horizontal Add and |
|
|
Saturate |
|
|
|
|
|
mmreg to mmreg |
0000 |
1111:0011 1000: 0000 0011:11 mmreg1 mmreg2 |
|
|
|
mem to mmreg |
0000 |
1111:0011 1000: 0000 0011: mod mmreg r/m |
|
|
|
xmmreg to xmmreg |
0110 |
0110:0000 1111:0011 1000: 0000 0011:11 xmmreg1 |
|
xmmreg2 |
|
|
|
|
mem to xmmreg |
0110 |
0110:0000 1111:0011 1000: 0000 0011: mod xmmreg r/m |
|
|
|
Vol. 2B B-89
INSTRUCTION FORMATS AND ENCODINGS
Table B-31. Formats and Encodings for SSSE3 Instructions (Contd.)
Instruction and Format |
|
Encoding |
|
|
|
PHADDW—Packed |
|
|
Horizontal Add Words |
|
|
|
|
|
mmreg to mmreg |
0000 |
1111:0011 1000: 0000 0001:11 mmreg1 mmreg2 |
|
|
|
mem to mmreg |
0000 |
1111:0011 1000: 0000 0001: mod mmreg r/m |
|
|
|
xmmreg to xmmreg |
0110 |
0110:0000 1111:0011 1000: 0000 0001:11 xmmreg1 |
|
xmmreg2 |
|
|
|
|
mem to xmmreg |
0110 |
0110:0000 1111:0011 1000: 0000 0001: mod xmmreg r/m |
|
|
|
PHSUBD—Packed |
|
|
Horizontal Subtract |
|
|
Double Words |
|
|
|
|
|
mmreg to mmreg |
0000 |
1111:0011 1000: 0000 0110:11 mmreg1 mmreg2 |
|
|
|
mem to mmreg |
0000 |
1111:0011 1000: 0000 0110: mod mmreg r/m |
|
|
|
xmmreg to xmmreg |
0110 |
0110:0000 1111:0011 1000: 0000 0110:11 xmmreg1 |
|
xmmreg2 |
|
|
|
|
mem to xmmreg |
0110 |
0110:0000 1111:0011 1000: 0000 0110: mod xmmreg r/m |
|
|
|
PHSUBSW—Packed |
|
|
Horizontal Subtract and |
|
|
Saturate |
|
|
|
|
|
mmreg to mmreg |
0000 |
1111:0011 1000: 0000 0111:11 mmreg1 mmreg2 |
|
|
|
mem to mmreg |
0000 |
1111:0011 1000: 0000 0111: mod mmreg r/m |
|
|
|
xmmreg to xmmreg |
0110 |
0110:0000 1111:0011 1000: 0000 0111:11 xmmreg1 |
|
xmmreg2 |
|
|
|
|
mem to xmmreg |
0110 |
0110:0000 1111:0011 1000: 0000 0111: mod xmmreg r/m |
|
|
|
PHSUBW—Packed |
|
|
Horizontal Subtract |
|
|
Words |
|
|
|
|
|
mmreg to mmreg |
0000 |
1111:0011 1000: 0000 0101:11 mmreg1 mmreg2 |
|
|
|
mem to mmreg |
0000 |
1111:0011 1000: 0000 0101: mod mmreg r/m |
|
|
|
xmmreg to xmmreg |
0110 |
0110:0000 1111:0011 1000: 0000 0101:11 xmmreg1 |
|
xmmreg2 |
|
|
|
|
mem to xmmreg |
0110 |
0110:0000 1111:0011 1000: 0000 0101: mod xmmreg r/m |
|
|
|
PMADDUBSW—Multiply |
|
|
and Add Packed Signed |
|
|
and Unsigned Bytes |
|
|
|
|
|
mmreg to mmreg |
0000 |
1111:0011 1000: 0000 0100:11 mmreg1 mmreg2 |
|
|
|
B-90 Vol. 2B
|
|
INSTRUCTION FORMATS AND ENCODINGS |
Table B-31. Formats and Encodings for SSSE3 Instructions (Contd.) |
||
|
|
|
Instruction and Format |
|
Encoding |
|
|
|
mem to mmreg |
0000 |
1111:0011 1000: 0000 0100: mod mmreg r/m |
|
|
|
xmmreg to xmmreg |
0110 |
0110:0000 1111:0011 1000: 0000 0100:11 xmmreg1 |
|
xmmreg2 |
|
|
|
|
mem to xmmreg |
0110 |
0110:0000 1111:0011 1000: 0000 0100: mod xmmreg r/m |
|
|
|
PMULHRSW—Packed |
|
|
Multiply HIgn with Round |
|
|
and Scale |
|
|
|
|
|
mmreg to mmreg |
0000 |
1111:0011 1000: 0000 1011:11 mmreg1 mmreg2 |
|
|
|
mem to mmreg |
0000 |
1111:0011 1000: 0000 1011: mod mmreg r/m |
|
|
|
xmmreg to xmmreg |
0110 |
0110:0000 1111:0011 1000: 0000 1011:11 xmmreg1 |
|
xmmreg2 |
|
|
|
|
mem to xmmreg |
0110 |
0110:0000 1111:0011 1000: 0000 1011: mod xmmreg r/m |
|
|
|
PSHUFB—Packed Shuffle |
|
|
Bytes |
|
|
|
|
|
mmreg to mmreg |
0000 |
1111:0011 1000: 0000 0000:11 mmreg1 mmreg2 |
|
|
|
mem to mmreg |
0000 |
1111:0011 1000: 0000 0000: mod mmreg r/m |
|
|
|
xmmreg to xmmreg |
0110 |
0110:0000 1111:0011 1000: 0000 0000:11 xmmreg1 |
|
xmmreg2 |
|
|
|
|
mem to xmmreg |
0110 |
0110:0000 1111:0011 1000: 0000 0000: mod xmmreg r/m |
|
|
|
PSIGNB—Packed Sign |
|
|
Bytes |
|
|
|
|
|
mmreg to mmreg |
0000 |
1111:0011 1000: 0000 1000:11 mmreg1 mmreg2 |
|
|
|
mem to mmreg |
0000 |
1111:0011 1000: 0000 1000: mod mmreg r/m |
|
|
|
xmmreg to xmmreg |
0110 |
0110:0000 1111:0011 1000: 0000 1000:11 xmmreg1 |
|
xmmreg2 |
|
|
|
|
mem to xmmreg |
0110 |
0110:0000 1111:0011 1000: 0000 1000: mod xmmreg r/m |
|
|
|
PSIGND—Packed Sign |
|
|
Double Words |
|
|
|
|
|
mmreg to mmreg |
0000 |
1111:0011 1000: 0000 1010:11 mmreg1 mmreg2 |
|
|
|
mem to mmreg |
0000 |
1111:0011 1000: 0000 1010: mod mmreg r/m |
|
|
|
xmmreg to xmmreg |
0110 |
0110:0000 1111:0011 1000: 0000 1010:11 xmmreg1 |
|
xmmreg2 |
|
|
|
|
mem to xmmreg |
0110 |
0110:0000 1111:0011 1000: 0000 1010: mod xmmreg r/m |
|
|
|
Vol. 2B B-91