VMX INSTRUCTION REFERENCE

VMfailValid(ErrorNumber):// executed only if there is a current VMCS CF ← 0;

PF ← 0;

AF ← 0;

ZF ← 1;

SF ← 0;

OF ← 0;

Set the VM-instruction error field to ErrorNumber;

The different VM-instruction error numbers are enumerated in Appendix J, “VM Instruction Error Numbers,” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3B.

5.3VMX INSTRUCTIONS

This section provides detailed descriptions of the VMX instructions.

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VMX INSTRUCTION REFERENCE

VMCALL—Call to VM Monitor

Description

This instruction allows guest software can make a call for service into an underlying VM monitor. The details of the programming interface for such calls are VMM-specific; this instruction does nothing more than cause a VM exit, registering the appropriate exit reason.

Use of this instruction in VMX root operation invokes an SMM monitor (see Section 24.16.2 in IA-32 Intel Architecture Software Developer’s Manual, Volume 3B). This invocation will activate the dual-monitor treatment of system-management interrupts (SMIs) and system-management mode (SMM) if it is not already active (see Section 24.16.6 in IA-32 Intel Architecture Software Developer’s Manual, Volume 3B).

Operation

IF not in VMX operation THEN #UD;

ELSIF in VMX non-root operation THEN VM exit;

ELSIF in SMM or if the valid bit in the IA32_SMM_MONITOR_CTL MSR is clear THEN VMfail(VMCALL executed in VMX root operation);

ELSIF (RFLAGS.VM = 1) OR (IA32_EFER.LMA = 1 and CS.L = 0) THEN #UD;

ELSIF CPL > 0 THEN #GP(0);

ELSIF dual-monitor treatment of SMIs and SMM is active

THEN perform an SMM VM exit (see Section 24.16.2

of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3B); ELSIF current-VMCS pointer is not valid

THEN VMfailInvalid;

ELSIF launch state of current VMCS is not clear THEN VMfailValid(VMCALL with non-clear VMCS);

ELSIF VM-exit control fields are not valid (see Section 24.16.6.1 of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3B)

THEN VMfailValid(VMCALL with invalid VM-exit control fields); ELSE

enter SMM;

read revision identifier in MSEG;

IF revision identifier does not match that supported by processor THEN

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VMX INSTRUCTION REFERENCE

leave SMM;

VMfailValid(VMCALL with incorrect MSEG revision identifier); ELSE

read SMM-monitor features field in MSEG (see Section 24.16.6.2,

in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3B); IF features field is invalid

THEN

leave SMM;

VMfailValid(VMCALL with invalid SMM-monitor features);

ELSE activate dual-monitor treatment of SMIs and SMM (see Section 24.16.6 in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume

3B);

FI;

FI;

FI;

Flags Affected

See the operation section and Section 5.2.

Use of Prefixes

Protected Mode Exceptions

Real-Address Mode Exceptions

Virtual-8086 Mode Exceptions

#UD If executed outside VMX non-root operation.

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VMX INSTRUCTION REFERENCE

Compatibility Mode Exceptions

#UD If executed outside VMX non-root operation.

64-Bit Mode Exceptions

#UD If executed outside VMX operation.

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VMX INSTRUCTION REFERENCE

VMCLEAR—Clear Virtual-Machine Control Structure

Description

This instruction applies to the VMCS whose VMCS region resides at the physical address contained in the instruction operand. The instruction ensures that VMCS data for that VMCS (some of these data may be currently maintained on the processor) are copied to the VMCS region in memory. It also initializes parts of the VMCS region (for example, it sets the launch state of that VMCS to clear). See Chapter 20, “Virtual-Machine Control Structures,” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3B.

The operand of this instruction is always 64 bits and is always in memory. If the operand is the current-VMCS pointer, then that pointer is made invalid (set to FFFFFFFF_FFFFFFFFH).

Note that the VMCLEAR instruction might not explicitly write any VMCS data to memory; the data may be already resident in memory before the VMCLEAR is executed.

Operation

IF (register operand) or (not in VMX operation) or (RFLAGS.VM = 1) or (IA32_EFER.LMA = 1 and CS.L = 0)

THEN #UD;

ELSIF in VMX non-root operation THEN VM exit;

ELSIF CPL > 0 THEN #GP(0); ELSE

addr ← contents of 64-bit in-memory operand; IF addr is not 4KB-aligned OR

(processor supports Intel 64 architecture and

addr sets any bits beyond the physical-address width) OR

(processor does not support Intel 64 architecture, addr sets any bits in the range 63:32) THEN VMfail(VMCLEAR with invalid physical address);

ELSIF addr = VMXON pointer

THEN VMfail(VMCLEAR with VMXON pointer); ELSE

ensure that data for VMCS referenced by the operand is in memory; initialize implementation-specific data in VMCS region;

launch state of VMCS referenced by the operand ← “clear”

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VMX INSTRUCTION REFERENCE

IF operand addr = current-VMCS pointer

THEN current-VMCS pointer ← FFFFFFFF_FFFFFFFFH;

FI;

VMsucceed;

FI;

FI;

Flags Affected

See the operation section and Section 5.2.

Use of Prefixes

Protected Mode Exceptions

Real-Address Mode Exceptions

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VMX INSTRUCTION REFERENCE

VMLAUNCH/VMRESUME—Launch/Resume Virtual Machine

Description

Effects a VM entry managed by the current VMCS.

•VMLAUNCH fails if the launch state of current VMCS is not “clear”. If the instruction is successful, it sets the launch state to “launched.”

•VMRESUME fails if the launch state of the current VMCS is not “launched.”

If VM entry is attempted, the logical processor performs a series of consistency checks as detailed in Chapter 22, “VM Entries,” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3B. Failure to pass checks on the VMX controls or on the host-state area passes control to the instruction following the VMLAUNCH or VMRESUME instruction. If these pass but checks on the guest-state area fail, the logical processor loads state from the host-state area of the VMCS, passing control to the instruction referenced by the RIP field in the host-state area.

VM entry is not allowed when events are blocked by MOV SS or POP SS. Neither VMLAUNCH nor VMRESUME should be used immediately after either MOV to SS or POP to SS.

Operation

IF (not in VMX operation) or (RFLAGS.VM = 1) or (IA32_EFER.LMA = 1 and CS.L = 0)

THEN #UD;

ELSIF in VMX non-root operation THEN VMexit;

ELSIF CPL > 0 THEN #GP(0);

ELSIF current-VMCS pointer is not valid THEN VMfailInvalid;

ELSIF events are being blocked by MOV SS

THEN VMfailValid(VM entry with events blocked by MOV SS); ELSIF (VMLAUNCH and launch state of current VMCS is not “clear”)

THEN VMfailValid(VMLAUNCH with non-clear VMCS);

ELSIF (VMRESUME and launch state of current VMCS is not “launched”) THEN VMfailValid(VMRESUME with non-launched VMCS);

ELSE

Check settings of VMX controls and host-state area; IF invalid settings

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VMX INSTRUCTION REFERENCE

THEN VMfailValid(VM entry with invalid VMX-control field(s)) or VMfailValid(VM entry with invalid host-state field(s)) or VMfailValid(VM entry with invalid executive-VMCS pointer)) or VMfailValid(VM entry with non-launched executive VMCS) or

VMfailValid(VM entry with executive-VMCS pointer not VMXON pointer) or

VMfailValid(VM entry with invalid VM-execution control fields in executive VMCS)

as appropriate;

ELSE

Attempt to load guest state and PDPTRs as appropriate; clear address-range monitoring;

IF failure in checking guest state or PDPTRs

THEN VM entry fails (see Section 22.7, in the

Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3B); ELSE

Attempt to load MSRs from VM-entry MSR-load area; IF failure

THEN VM entry fails (see Section 22.7, in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3B);

ELSE

IF VMLAUNCH

THEN launch state of VMCS ← “launched”;

FI;

IF in SMM and “entry to SMM” VM-entry control is 0 THEN

IF “deactivate dual-monitor treatment” VM-entry control is 0

THEN SMM-transfer VMCS pointer ← current-VMCS pointer;

FI;

IF executive-VMCS pointer is VMX pointer THEN current-VMCS pointer ← VMCS-link pointer;

ELSE current-VMCS pointer ← executive-VMCS pointer;

FI;

leave SMM;

FI;

VM entry succeeds;

FI;

FI;

FI;

FI;

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VMX INSTRUCTION REFERENCE

Further details of the operation of the VM-entry appear in Chapter 22 of IA-32 Intel Architecture Software Developer’s Manual, Volume 3B.

Flags Affected

See the operation section and Section 5.2.

Use of Prefixes

Protected Mode Exceptions

Real-Address Mode Exceptions

Virtual-8086 Mode Exceptions

Compatibility Mode Exceptions

64-Bit Mode Exceptions

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VMX INSTRUCTION REFERENCE

VMPTRLD—Load Pointer to Virtual-Machine Control Structure

Description

Marks the current-VMCS pointer valid and loads it with the physical address in the instruction operand. The instruction fails if its operand is not properly aligned, sets unsupported physical-address bits, or is equal to the VMXON pointer. In addition, the instruction fails if the 32 bits in memory referenced by the operand do not match the VMCS revision identifier supported by this processor.1

The operand of this instruction is always 64 bits and is always in memory.

Operation

IF (register operand) or (not in VMX operation) or (RFLAGS.VM = 1) or (IA32_EFER.LMA = 1 and CS.L = 0)

THEN #UD;

ELSIF in VMX non-root operation THEN VMexit;

ELSIF CPL > 0 THEN #GP(0); ELSE

addr ← contents of 64-bit in-memory source operand; IF addr is not 4KB-aligned OR

(processor supports Intel 64 architecture and

addr sets any bits beyond the processor’s physical-address width) OR

processor does not support Intel 64 architecture and addr sets any bits in the range 63:32 THEN VMfail(VMPTRLD with invalid physical address);

ELSIF addr = VMXON pointer

THEN VMfail(VMPTRLD with VMXON pointer); ELSE

rev ← 32 bits located at physical address addr;

IF rev ≠ VMCS revision identifier supported by processor

THEN VMfail(VMPTRLD with incorrect VMCS revision identifier); ELSE

current-VMCS pointer ← addr; VMsucceed;

FI;

1.Software should consult the VMX capability MSR VMX_BASIC to discover the VMCS revision identifier supported by this processor (see Appendix G, “VMX Capability Reporting Facility,” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3B).

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VMX INSTRUCTION REFERENCE

FI;

FI;

Flags Affected

See the operation section and Section 5.2.

Use of Prefixes

Protected Mode Exceptions

Real-Address Mode Exceptions

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VMX INSTRUCTION REFERENCE

VMPTRST—Store Pointer to Virtual-Machine Control Structure

Description

Stores the current-VMCS pointer into a specified memory address. The operand of this instruction is always 64 bits and is always in memory.

Operation

IF (register operand) or (not in VMX operation) or (RFLAGS.VM = 1) or (IA32_EFER.LMA = 1 and CS.L = 0)

THEN #UD;

ELSIF in VMX non-root operation THEN VMexit;

ELSIF CPL > 0 THEN #GP(0); ELSE

64-bit in-memory destination operand ← current-VMCS pointer; VMsucceed;

FI;

Flags Affected

See the operation section and Section 5.2.

Use of Prefixes

Protected Mode Exceptions

#GP(0) If the current privilege level is not 0.

If the memory destination operand effective address is outside the CS, DS, ES, FS, or GS segment limit.

5-16 Vol. 2B

Real-Address Mode Exceptions

Virtual-8086 Mode Exceptions

Compatibility Mode Exceptions

64-Bit Mode Exceptions

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VMX INSTRUCTION REFERENCE

VMREAD—Read Field from Virtual-Machine Control Structure

Description

Reads a specified field from the VMCS and stores it into a specified destination operand (register or memory).

The specific VMCS field is identified by the VMCS-field encoding contained in the register source operand. Outside IA-32e mode, the source operand has 32 bits, regardless of the value of CS.D. In 64-bit mode, the source operand has 64 bits; however, if bits 63:32 of the source operand are not zero, VMREAD will fail due to an attempt to access an unsupported VMCS component (see operation section).

The effective size of the destination operand, which may be a register or in memory, is always 32 bits outside IA-32e mode (the setting of CS.D is ignored with respect to operand size) and 64 bits in 64-bit mode. If the VMCS field specified by the source operand is shorter than this effective operand size, the high bits of the destination operand are cleared to 0. If the VMCS field is longer, then the high bits of the field are not read.

Note that any faults resulting from accessing a memory destination operand can occur only after determining, in the operation section below, that the VMCS pointer is valid and that the specified VMCS field is supported.

Operation

IF (not in VMX operation) or (RFLAGS.VM = 1) or (IA32_EFER.LMA = 1 and CS.L = 0)

THEN #UD;

ELSIF in VMX non-root operation THEN VMexit;

ELSIF CPL > 0 THEN #GP(0);

ELSIF current-VMCS pointer is not valid THEN VMfailInvalid;

ELSIF register source operand does not correspond to any VMCS field

THEN VMfailValid(VMREAD/VMWRITE from/to unsupported VMCS component); ELSE

DEST ← contents of VMCS field indexed by register source operand; VMsucceed;

FI;

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VMX INSTRUCTION REFERENCE

Flags Affected

See the operation section and Section 5.2.

Use of Prefixes

Protected Mode Exceptions

Real-Address Mode Exceptions

Virtual-8086 Mode Exceptions

#UD The VMREAD instruction is not recognized in virtual-8086 mode.

Compatibility Mode Exceptions

#UD The VMREAD instruction is not recognized in compatibility mode.

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VMX INSTRUCTION REFERENCE

64-Bit Mode Exceptions

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VMX INSTRUCTION REFERENCE

VMRESUME—Resume Virtual Machine

See VMLAUNCH/VMRESUME—Launch/Resume Virtual Machine.

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VMX INSTRUCTION REFERENCE

VMWRITE—Write Field to Virtual-Machine Control Structure

Description

Writes to a specified field in the VMCS specified by a secondary source operand (register only) using the contents of a primary source operand (register or memory).

The VMCS field is identified by the VMCS-field encoding contained in the register secondary source operand. Outside IA-32e mode, the secondary source operand is always 32 bits, regardless of the value of CS.D. In 64-bit mode, the secondary source operand has 64 bits; however, if bits 63:32 of the secondary source operand are not zero, VMWRITE will fail due to an attempt to access an unsupported VMCS component (see operation section).

The effective size of the primary source operand, which may be a register or in memory, is always 32 bits outside IA-32e mode (the setting of CS.D is ignored with respect to operand size) and 64 bits in 64-bit mode. If the VMCS field specified by the secondary source operand is shorter than this effective operand size, the high bits of the primary source operand are ignored. If the VMCS field is longer, then the high bits of the field are cleared to 0.

Note that any faults resulting from accessing a memory source operand occur after determining, in the operation section below, that the VMCS pointer is valid but before determining if the destination VMCS field is supported.

Operation

IF (not in VMX operation) or (RFLAGS.VM = 1) or (IA32_EFER.LMA = 1 and CS.L = 0)

THEN #UD;

ELSIF in VMX non-root operation THEN VMexit;

ELSIF CPL > 0 THEN #GP(0);

ELSIF current-VMCS pointer is not valid THEN VMfailInvalid;

ELSIF register destination operand does not correspond to any VMCS field

THEN VMfailValid(VMREAD/VMWRITE from/to unsupported VMCS component); ELSIF VMCS field indexed by register destination operand is read-only)

THEN VMfailValid(VMWRITE to read-only VMCS component); ELSE

VMCS field indexed by register destination operand ← SRC;

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VMX INSTRUCTION REFERENCE

VMsucceed;

FI;

Flags Affected

See the operation section and Section 5.2.

Use of Prefixes

Protected Mode Exceptions

Real-Address Mode Exceptions

Virtual-8086 Mode Exceptions

Compatibility Mode Exceptions

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VMX INSTRUCTION REFERENCE

64-Bit Mode Exceptions

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VMX INSTRUCTION REFERENCE

VMXOFF—Leave VMX Operation

Description

Takes the logical processor out of VMX operation, unblocks INIT signals, re-enables A20M, and clears any address-range monitoring.1

Operation

IF (not in VMX operation) or (RFLAGS.VM = 1) or (IA32_EFER.LMA = 1 and CS.L = 0)

THEN #UD;

ELSIF in VMX non-root operation THEN VMexit;

ELSIF CPL > 0 THEN #GP(0);

ELSIF dual-monitor treatment of SMIs and SMM is active

THEN VMfail(VMXOFF under dual-monitor treatment of SMIs and SMM); ELSE

leave VMX operation; unblock INIT;

unblock and enable A20M; clear address-range monitoring; VMsucceed;

FI;

Flags Affected

See the operation section and Section 5.2.

Use of Prefixes

1.See the information on MONITOR/MWAIT in Chapter 7, “Multiple-Processor Management,” of the

Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A.

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VMX INSTRUCTION REFERENCE

Protected Mode Exceptions

Real-Address Mode Exceptions

Virtual-8086 Mode Exceptions

#UD The VMXOFF instruction is not recognized in virtual-8086 mode.

Compatibility Mode Exceptions

#UD The VMXOFF instruction is not recognized in compatibility mode.

64-Bit Mode Exceptions

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VMX INSTRUCTION REFERENCE

VMXON—Enter VMX Operation

Description

Puts the logical processor in VMX operation with no current VMCS, blocks INIT signals, disables A20M, and clears any address-range monitoring established by the MONITOR instruction.1

The operand of this instruction is a 4KB-aligned physical address (the VMXON pointer) that references the VMXON region, which the logical processor may use to support VMX operation. This operand is always 64 bits and is always in memory.

Operation

IF (register operand) or (CR4.VMXE = 0) or (CR0.PE = 0) or (RFLAGS.VM = 1) or (IA32_EFER.LMA = 1 and CS.L = 0)

THEN #UD;

ELSIF not in VMX operation THEN

IF (CPL > 0) or (in A20M mode) or

(the values of CR0 and CR4 are supported in VMX operation2) or (bit 0 (lock bit) of IA32_FEATURE_CONTROL MSR is clear) or (bit 2 of IA32_FEATURE_CONTROL MSR is clear)

THEN #GP(0); ELSE

addr ← contents of 64-bit in-memory source operand; IF addr is not 4KB-aligned or

(processor supports Intel 64 architecture and

addr sets any bits beyond the VMX physical-address width) or (processor does not support Intel 64 architecture and

addr sets any bits in the range 63:32) THEN VMfailInvalid;

ELSE

rev ← 32 bits located at physical address addr;

IF rev ≠ VMCS revision identifier supported by processor THEN VMfailInvalid;

1.See the information on MONITOR/MWAIT in Chapter 7, “Multiple-Processor Management,” of the

Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A.

2.See Section 19.8 of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3B.

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VMX INSTRUCTION REFERENCE

ELSE

current-VMCS pointer ← FFFFFFFF_FFFFFFFFH; enter VMX operation;

block INIT signals;

block and disable A20M;

clear address-range monitoring; VMsucceed;

FI;

FI;

FI;

ELSIF in VMX non-root operation THEN VMexit;

ELSIF CPL > 0 THEN #GP(0);

ELSE VMfail(“VMXON executed in VMX root operation”);

FI;

Flags Affected

See the operation section and Section 5.2.

Use of Prefixes

Protected Mode Exceptions

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Real-Address Mode Exceptions

#UD The VMXON instruction is not recognized in real-address mode.

Virtual-8086 Mode Exceptions

#UD The VMXON instruction is not recognized in virtual-8086 mode.

Compatibility Mode Exceptions

#UD The VMXON instruction is not recognized in compatibility mode.

64-Bit Mode Exceptions

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VMX INSTRUCTION REFERENCE

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