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Файл:Лаб2012 / 253667.pdf
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- •5.1 Overview
- •5.2 Conventions
- •5.3 VMX Instructions
- •A.1 Using Opcode Tables
- •A.2 Key to Abbreviations
- •A.2.1 Codes for Addressing Method
- •A.2.2 Codes for Operand Type
- •A.2.3 Register Codes
- •A.2.4 Opcode Look-up Examples for One, Two, and Three-Byte Opcodes
- •A.2.4.1 One-Byte Opcode Instructions
- •A.2.4.2 Two-Byte Opcode Instructions
- •A.2.4.3 Three-Byte Opcode Instructions
- •A.2.5 Superscripts Utilized in Opcode Tables
- •A.3 One, Two, and THREE-Byte Opcode Maps
- •A.4 Opcode Extensions For One-Byte And Two-byte Opcodes
- •A.4.1 Opcode Look-up Examples Using Opcode Extensions
- •A.4.2 Opcode Extension Tables
- •A.5 Escape Opcode Instructions
- •A.5.1 Opcode Look-up Examples for Escape Instruction Opcodes
- •A.5.2 Escape Opcode Instruction Tables
- •A.5.2.1 Escape Opcodes with D8 as First Byte
- •A.5.2.2 Escape Opcodes with D9 as First Byte
- •A.5.2.3 Escape Opcodes with DA as First Byte
- •A.5.2.4 Escape Opcodes with DB as First Byte
- •A.5.2.5 Escape Opcodes with DC as First Byte
- •A.5.2.6 Escape Opcodes with DD as First Byte
- •A.5.2.7 Escape Opcodes with DE as First Byte
- •A.5.2.8 Escape Opcodes with DF As First Byte
- •Appendix B Instruction Formats and Encodings
- •B.1 Machine Instruction Format
- •B.1.1 Legacy Prefixes
- •B.1.2 REX Prefixes
- •B.1.3 Opcode Fields
- •B.1.4 Special Fields
- •B.1.4.1 Reg Field (reg) for Non-64-Bit Modes
- •B.1.4.2 Reg Field (reg) for 64-Bit Mode
- •B.1.4.3 Encoding of Operand Size (w) Bit
- •B.1.4.4 Sign-Extend (s) Bit
- •B.1.4.5 Segment Register (sreg) Field
- •B.1.4.6 Special-Purpose Register (eee) Field
- •B.1.4.7 Condition Test (tttn) Field
- •B.1.4.8 Direction (d) Bit
- •B.1.5 Other Notes
- •B.2 General-Purpose Instruction Formats and Encodings for Non-64-Bit Modes
- •B.2.1 General Purpose Instruction Formats and Encodings for 64-Bit Mode
- •B.3 Pentium® Processor Family Instruction Formats and Encodings
- •B.4 64-bit Mode Instruction Encodings for SIMD Instruction Extensions
- •B.5 MMX Instruction Formats and Encodings
- •B.5.1 Granularity Field (gg)
- •B.5.2 MMX Technology and General-Purpose Register Fields (mmxreg and reg)
- •B.5.3 MMX Instruction Formats and Encodings Table
- •B.6 P6 Family INstruction Formats and Encodings
- •B.7 SSE Instruction Formats and Encodings
- •B.8 SSE2 Instruction Formats and Encodings
- •B.8.1 Granularity Field (gg)
- •B.9 SSE3 Formats and Encodings Table
- •B.10 SSSE3 Formats and Encoding Table
- •B.11 Special Encodings for 64-Bit Mode
- •B.12 Floating-Point Instruction Formats and Encodings
- •B.13 VMX Instructions
- •Appendix C InteL® C/C++ Compiler Intrinsics and Functional Equivalents
- •C.1 Simple Intrinsics
- •Intel Sales Offices
- •Index for Volumes 2A & 2B
INSTRUCTION FORMATS AND ENCODINGS
B.3 PENTIUM® PROCESSOR FAMILY INSTRUCTION FORMATS AND ENCODINGS
The following table shows formats and encodings introduced by the Pentium processor family.
Table B-16. Pentium Processor Family Instruction Formats and Encodings,
Non-64-Bit Modes
Instruction and Format |
Encoding |
|
|
CMPXCHG8B – Compare and Exchange 8 Bytes |
|
|
|
EDX:EAX with memory64 |
0000 1111 : 1100 0111 : mod 001 r/m |
|
|
Table B-17. Pentium Processor Family Instruction Formats and Encodings, 64-Bit
Mode
Instruction and Format |
|
Encoding |
|
|
|
CMPXCHG8B/CMPXCHG16B – Compare and |
|
|
Exchange Bytes |
|
|
|
|
|
EDX:EAX with memory64 |
0000 |
1111 : 1100 0111 : mod 001 r/m |
|
|
|
RDX:RAX with memory128 |
0100 |
10XB 0000 1111 : 1100 0111 : mod |
|
001 r/m |
|
|
|
|
Vol. 2B B-53
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