
- •V. Ya. Krakovsky, m. B. Fesenko
- •In Computer Systems and Networks
- •Contents
- •Preface
- •Introduction
- •Module I. Basic Components of Digital Computers
- •1. The Structure of a Digital Computer
- •1.1. Introduction to Digital Computers
- •Questions for Self-Testing
- •1.2. The Computer Work Stages Implementation Sequence
- •Questions for Self-Testing
- •1.3. Register Gating and Timing of Data Transfers
- •Questions for Self-Testing
- •1.4. Computer Interface Organization
- •Questions for Self-Testing
- •1.5. Computer Control Organization
- •Questions for Self-Testing
- •1.6. Function and Construction of Computer Memory
- •Questions for Self-Testing
- •1.7. Architecturally-Structural Memory Organization Features
- •Questions for Self-Testing
- •2. Data processing fundamentals in digital computers
- •2.1. Element Base Development Influence on Data Processing
- •Questions for Self-Testing
- •2.2. Computer Arithmetic
- •Questions for Self-Testing
- •2.3. Operands Multiplication Operation
- •Questions for Self-Testing
- •2.4. Integer Division
- •Questions for Self-Testing
- •2.5. Floating-Point Numbers and Operations
- •Questions for Self-Testing
- •Questions for Self-Testing on Module I
- •Problems for Self-Testing on Module I
- •Module II. Digital computer organization
- •3. Processors, Memory, and the Evolution System of Instructions
- •3.1. Cisc and risc Microprocessors
- •Questions for Self-Testing
- •3.2. Pipelining
- •Questions for Self-Testing
- •3.3. Interrupts
- •Questions for Self-Testing
- •3.4. Superscalar Processing
- •Questions for Self-Testing
- •3.5. Designing Instruction Formats
- •Questions for Self-Testing
- •3.6. Building a Stack Frame
- •Questions for Self-Testing
- •4. The Structures of Digital Computers
- •4.1. Microprocessors, Microcontrollers, and Systems
- •Questions for Self-Testing
- •4.2. Stack Computers
- •Questions for Self-Testing
- •Questions for Self-Testing
- •4.4. Features of Organization Structure of the Pentium Processors
- •Questions for Self-Testing
- •4.5. Computers Systems on a Chip
- •Multicore Microprocessors.
- •Questions for Self-Testing
- •4.6. Principles of Constructing Reconfigurable Computing Systems
- •Questions for Self-Testing
- •4.7. Types of Digital Computers
- •Questions for Self-Testing
- •Questions for Self-Testing on Module II
- •Problems for Self-Testing on Module II
- •Module III. Parallelism and Scalability
- •5. Super Scalar Processors
- •5.1. The sparc Architecture
- •Questions for Self-Testing
- •5.2. Sparc Addressing Modes and Instruction Set
- •Questions for Self-Testing
- •5.3. Floating-Point on the sparc
- •Questions for Self-Testing
- •5.4. The sparc Computers Family
- •Questions for Self-Testing
- •6. Cluster Superscalar Processors
- •6.1. The Power Architecture
- •Questions for Self-Testing
- •6.2. Multithreading
- •Questions for Self-Testing
- •6.3. Power Microprocessors
- •Questions for Self-Testing
- •6.4. Microarchitecture Level Power-Performance Fundamentals
- •Questions for Self-Testing
- •6.5. The Design Space of Register Renaming Techniques
- •Questions for Self-Testing
- •Questions for Self-Testing on Module III
- •Problems for Self-Testing on Module III
- •Module IV. Explicitly Parallel Instruction Computing
- •7. The itanium processors
- •7.1. Parallel Instruction Computing and Instruction Level Parallelism
- •Questions for Self-Testing
- •7.2. Predication
- •Questions for Self-Testing
- •Questions for Self-Testing
- •7.4. The Itanium Processor Microarchitecture
- •Questions for Self-Testing
- •7.5. Deep Pipelining (10 stages)
- •Questions for Self-Testing
- •7.6. Efficient Instruction and Operand Delivery
- •Instruction bundles capable of full-bandwidth dispersal
- •Questions for Self-Testing
- •7.7. High ilp Execution Core
- •Questions for Self-Testing
- •7.8. The Itanium Organization
- •Implementation of cache hints
- •Questions for Self-Testing
- •7.9. Instruction-Level Parallelism
- •Questions for Self-Testing
- •7.10. Global Code Scheduler and Register Allocation
- •Questions for Self-Testing
- •8. Digital computers on the basic of vliw
- •Questions for Self-Testing
- •8.2. Synthesis of Parallelism and Scalability
- •Questions for Self-Testing
- •8.3. The majc Architecture
- •Questions for Self-Testing
- •8.4. Scit – Ukrainian Supercomputer Project
- •Questions for Self-Testing
- •8.5. Components of Cluster Supercomputer Architecture
- •Questions for Self-Testing
- •Questions for Self-Testing on Module IV
- •Problems for Self-Testing on Module IV
- •Conclusion
- •List of literature
- •Index and Used Abbreviations
- •03680. Київ-680, проспект Космонавта Комарова, 1.
Questions for Self-Testing
1. What are the peculiarities of the supercomputer SCIT structure?
2. What is the purpose of а local control network?
3. What is the purpose of а local monitor network?
4. What functions does а local data network perform?
5. What are the differences between SCIT supercomputer systems and server cluster systems?
6. What are the requirements to the cluster node?
7. Why is a “short” conveyer preferable rather than a “long” conveyer in solving parallel problems?
8. What causes throughput decrease when hyperthreading parallel problems?
9. Which memory system organization is preferable for solving parallel problems in a cluster?
10. What are the requirements to the main memory of an SCIT supercomputer?
11. What does the throughput of an SCIT cluster supercomputer depend on?
12. What are the basic features of SCIT cluster systems?
13. What are the components of the MPI procedure?
14. Is it possible to create libraries of parallel programs on the basis of the MPI? Why?
15. Is the MPI an interface dependent on computer architecture?
Questions for Self-Testing on Module IV
1. What are explicitly parallel instruction computing and ILP?
2. What is the Itanium processor microarchitecture?
3. What is instruction level parallelism?
4. What are scheduling and speculation?
5. What is control speculation?
6. How to use a register model?
7. What is software pipelining?
8. What is the IA-64 virtual memory model?
9. What is the IA-64 floating-point architecture?
10. What is the Itanium processor microarchitecture?
11. What is the EPIC hardware?
12. What is dynamic hardware for runtime optimization?
13. What is efficient instruction and operand delivery?
14. What is the high ILP execution core?
15. What are rotating registers?
16. What is the Itanium server 16-way architecture?
17. What is the chip set architecture?
18. What is the MAJC architecture?
19. How do virtual channels work?
20. What is thread support?
21. What are the architectural features?
22. What is an instruction set?
23. What is the SCIT – Ukrainian supercomputer project?
24. What is the development ideology?
25. What are the architecture components of a cluster supercomputer?
26. What does the choosing of architecture features for a supercomputer project consist in?
Problems for Self-Testing on Module IV
1. How is it possible to replace a library function with a function of the same name without losing the possibility of evoking the initial function from the substitute one?
2. Is it possible for processes belonging to different communicators to communicate with one another?
3. Is it true that no two processes of a program can have the same number?
4. How is it possible to determine size of the buffer in the MPI needed to receive a message?
5. In a parallel cycle is evoked a function which, in turn, has a parallel cycle in its body. How will this construct be processed?
6. Make a study of the inherent parallelism in Horner’s method for evaluation of polynomial in a given point.
7. Give examples of different algorithms designated for solving different problems but having the same graphs.
8. Using unary and binary operations, build a graph of the square root calculation algorithm and calculate the possibilities of branching.
9. Is it possible for a one-dimensional vector cycle to run in the scalar mode faster than in the vector mode?
10. Why, in conveyer functional units, is the reacting duration of different stages made the same?
11. What is the relationship between the time slot and the clock frequency?
12. Why is the peak throughput of a conveyer computer beyond practical reach?
13. Which processor should have a more “intellectual” compiler for generation of efficient programs: superscalar or VLIW?
14. Why is the common bus not used for uniting a large number of processors?
15. Let a specially designed processor be a matrix of one-bit processors operating in a synchronized manner. What kind of problems can be efficiently solved by this specially designed processor?