- •V. Ya. Krakovsky, m. B. Fesenko
- •In Computer Systems and Networks
- •Contents
- •Preface
- •Introduction
- •Module I. Basic Components of Digital Computers
- •1. The Structure of a Digital Computer
- •1.1. Introduction to Digital Computers
- •Questions for Self-Testing
- •1.2. The Computer Work Stages Implementation Sequence
- •Questions for Self-Testing
- •1.3. Register Gating and Timing of Data Transfers
- •Questions for Self-Testing
- •1.4. Computer Interface Organization
- •Questions for Self-Testing
- •1.5. Computer Control Organization
- •Questions for Self-Testing
- •1.6. Function and Construction of Computer Memory
- •Questions for Self-Testing
- •1.7. Architecturally-Structural Memory Organization Features
- •Questions for Self-Testing
- •2. Data processing fundamentals in digital computers
- •2.1. Element Base Development Influence on Data Processing
- •Questions for Self-Testing
- •2.2. Computer Arithmetic
- •Questions for Self-Testing
- •2.3. Operands Multiplication Operation
- •Questions for Self-Testing
- •2.4. Integer Division
- •Questions for Self-Testing
- •2.5. Floating-Point Numbers and Operations
- •Questions for Self-Testing
- •Questions for Self-Testing on Module I
- •Problems for Self-Testing on Module I
- •Module II. Digital computer organization
- •3. Processors, Memory, and the Evolution System of Instructions
- •3.1. Cisc and risc Microprocessors
- •Questions for Self-Testing
- •3.2. Pipelining
- •Questions for Self-Testing
- •3.3. Interrupts
- •Questions for Self-Testing
- •3.4. Superscalar Processing
- •Questions for Self-Testing
- •3.5. Designing Instruction Formats
- •Questions for Self-Testing
- •3.6. Building a Stack Frame
- •Questions for Self-Testing
- •4. The Structures of Digital Computers
- •4.1. Microprocessors, Microcontrollers, and Systems
- •Questions for Self-Testing
- •4.2. Stack Computers
- •Questions for Self-Testing
- •Questions for Self-Testing
- •4.4. Features of Organization Structure of the Pentium Processors
- •Questions for Self-Testing
- •4.5. Computers Systems on a Chip
- •Multicore Microprocessors.
- •Questions for Self-Testing
- •4.6. Principles of Constructing Reconfigurable Computing Systems
- •Questions for Self-Testing
- •4.7. Types of Digital Computers
- •Questions for Self-Testing
- •Questions for Self-Testing on Module II
- •Problems for Self-Testing on Module II
- •Module III. Parallelism and Scalability
- •5. Super Scalar Processors
- •5.1. The sparc Architecture
- •Questions for Self-Testing
- •5.2. Sparc Addressing Modes and Instruction Set
- •Questions for Self-Testing
- •5.3. Floating-Point on the sparc
- •Questions for Self-Testing
- •5.4. The sparc Computers Family
- •Questions for Self-Testing
- •6. Cluster Superscalar Processors
- •6.1. The Power Architecture
- •Questions for Self-Testing
- •6.2. Multithreading
- •Questions for Self-Testing
- •6.3. Power Microprocessors
- •Questions for Self-Testing
- •6.4. Microarchitecture Level Power-Performance Fundamentals
- •Questions for Self-Testing
- •6.5. The Design Space of Register Renaming Techniques
- •Questions for Self-Testing
- •Questions for Self-Testing on Module III
- •Problems for Self-Testing on Module III
- •Module IV. Explicitly Parallel Instruction Computing
- •7. The itanium processors
- •7.1. Parallel Instruction Computing and Instruction Level Parallelism
- •Questions for Self-Testing
- •7.2. Predication
- •Questions for Self-Testing
- •Questions for Self-Testing
- •7.4. The Itanium Processor Microarchitecture
- •Questions for Self-Testing
- •7.5. Deep Pipelining (10 stages)
- •Questions for Self-Testing
- •7.6. Efficient Instruction and Operand Delivery
- •Instruction bundles capable of full-bandwidth dispersal
- •Questions for Self-Testing
- •7.7. High ilp Execution Core
- •Questions for Self-Testing
- •7.8. The Itanium Organization
- •Implementation of cache hints
- •Questions for Self-Testing
- •7.9. Instruction-Level Parallelism
- •Questions for Self-Testing
- •7.10. Global Code Scheduler and Register Allocation
- •Questions for Self-Testing
- •8. Digital computers on the basic of vliw
- •Questions for Self-Testing
- •8.2. Synthesis of Parallelism and Scalability
- •Questions for Self-Testing
- •8.3. The majc Architecture
- •Questions for Self-Testing
- •8.4. Scit – Ukrainian Supercomputer Project
- •Questions for Self-Testing
- •8.5. Components of Cluster Supercomputer Architecture
- •Questions for Self-Testing
- •Questions for Self-Testing on Module IV
- •Problems for Self-Testing on Module IV
- •Conclusion
- •List of literature
- •Index and Used Abbreviations
- •03680. Київ-680, проспект Космонавта Комарова, 1.
Preface
The discipline “Digital Computers” is one of the basic disciplines in the system of knowledge and skills forming the Bachelor, Specialist, and Master of Science in the speciality “Computer Systems and Networks.” The objectives of teaching the discipline are to give the students theoretical and practical grounding in the development and use of up-to-date complex digital computers.
In studying the discipline, the students are supposed to master the science and technology development tendencies in the area of complex digital computers, to get acquainted with the digital computers problems that are important now, basic terms and definitions, and digital computers synthesis and analysis methods.
The discipline “Digital Computers” is in close connection with such fields of knowledge as “Higher Mathematics,” “Discrete Mathematics,” “Physics,” “Applied Theory of Digital Machines,” “Computer Circuit Engineering,” “Computer Electronics,” “Computer Architecture,” “Reliability, Control, Diagnostics, and Exploitation of Computer,” and “Programming.” The discipline will be used and further studied in most profession-oriented disciplines.
This Study Guide has been compiled with the use of original English references [1-11, 13-18, and 22-37]. When using the Study Guide for training within the European Credit Transfer System of education, its contents may be divided into the following modules: M1 – chapters 1 and 2, M2 – chapters 3 and 4, M3 – chapters 5 and 6, and M4 – chapters 7 and 8.
Special gratitude is to the English language adviser O.Ye. Bugaiov, an associate professor of NAU for his thorough review of the entire manuscript, which significantly improved the Study Guide. Particular gratitude is to the reviewers: Prof. V.P. Boyun, Corresponding member of NAS of Ukraine, Dr. Sci. (Eng.), Head of the Department of Controlling Machines of Glushkov Institute of Cybernetics of NAS of Ukraine; Prof. G.M. Lutsky, Dr. Sci. (Eng.), Head of the Computer Engineering Department of National Technical University of Ukraine “Kyiv Polytechnic Institute” and two associate professors of this department: V.L. Selivanov, Cand. Sci. (Eng.), and A.M. Sergienko, Cand. Sci. (Eng.); and V.M. Yefimets, Cand. Sci. (Eng.), an associate professor of the Computer Systems and Networks Department of the State University of Information Communication Technologies of Ukraine. The same gratitude is to M.A. Vinogradov, professor of NAU for his suggestions to improve the book. Any comments and suggestions are welcomed.
Introduction
The computer industry continues to be the fastest-growing major industry. The sales of computers increase every year, and the booming personal computer market has further supplemented the size of the overall computer industry.
Personal computers make possible expanding new application areas for computers because of their low cost, reliability, small size, and low weight. These small computers are able to calculate at a rate of billions of operations per second and offer computing power, which was available in only the larger computers as recently as 10 years ago. The places where small computers can be used appear endless: such areas as process control, medical monitoring, production testing, scientific instrument recording, store checkout systems, and automobile test and evaluation systems were among the first to appear. In fact, computers now route our long-distance telephone calls, process and issue the checks in our banks, schedule our planes and trains, make our weather forecasts, predict and process our elections, and figure in so many things that entire books may be written just documenting the types of applications.
The book contains preface, introduction, four modules of two chapters each, and conclusion.
Module I describes the structure and basic components of a digital computer. Virtual memory systems are rapidly increasing in numbers. Many new computer designs, including high-performance microcomputer systems, have virtual-memory capability as a part of their basic hardware and operating software. Others are designed in such a way as to facilitate its implementation. Memory management and cache control both have to do with how an operating system controls a task's use of memory. Most microprocessors have hardware support for virtual memory, allowing a task's addressable memory to be larger than the real memory on a machine, as well as allowing several tasks to share that memory. Caches are small (but fast) memories that hold copies of the data in the most frequently used memory locations. The ability to perform floating-point computations in hardware is particularly important given the fact that microprocessors are commonly used to build workstations for scientific and engineering use.
Module II provides an introduction to RISC and CISC digital computers. The history of CISC designs showed an increasing complexity in the instructions included on these machines. The motivation behind the inclusion of these instructions was the belief that they would help support the increasingly used high-level languages. RISC designs can be viewed as a reaction to the complexity of CISC processors. The main empirical data used to justify the approach is the observation that most of the complex instructions on a CISC machine, precisely those that complicate its implementation the most, are the instructions that are used least, and their presence do not justify their cost.
Parallelism and scalability are considered in Module III. SPARC is an important entry in the RISC scene from a commercial point of view, since it represents a major commitment to RISC by the leading workstation vendor. SPARC and MIPS represent rival designs of architectures that are designed with very similar goals and general design criteria. Nevertheless, there are a number of crucial technical differences, including the use of register windows and double indexing in the SPARC and the larger addressing offsets and different pipeline approach of the MIPS.
Module IV is devoted to introducing the IA-64 architecture of digital computers. This Module describes the key concepts and mechanisms provided in the instruction set at a high level, along with the main motivations behind the inclusion of these mechanisms. Virtual memory support in IA-64 includes better support for sharing (up to and including support for a single address space) that we expect to happen with the large increase in addressing that comes with a 64-bit architecture. This Module describes also the internal structure of the first processor to implement the IA-64 instruction set. It emphasizes how the processor supports EPIC constructs such as predication, control and data speculation, and multiway branches. The compiler is a key component of performance in an Itanium processor-based system. The structure and considerations for the code generation phase of a compiler is described in this module. The module discusses the system architecture and the partitioning and clustering structure of this large system with a remote and Remote Access Service features to support enterprise applications. The module describes also a set of capabilities for detecting, containing, reporting, and recovering from hardware failures in processor and external buses. These features are important in the enterprise-computing application area that is a key target of the initial Itanium processor systems.
Questions for self-testing are presented at the end of each paragraph and, also, other questions and problems to be solved are presented at the end of each module.
