Questions for Self-Testing

1. What is the purpose of register renaming techniques?

2. What are the types of data dependencies?

3. What are there four main dimensions of register renaming?

4. What is the essence of the basic principle of register renaming?

5. Describe the evolution of register renaming techniques.

6. What is the essence of the Tomasulo’s Algorithm?

7. What are the four fundamentally different ways to implement rename buffers?

8. In which of four possible states may each physical register of the merged architectural and rename register file be at any time?

9. How can we determine possible changes in the states of the physical registers during instruction processing with the help of allowed transitions indicated in the state transition diagram?

10. What is the essence of the instruction shelving principle?

11. What are two revolving pointers in the ROB used for?

12. When does the ROB allow instructions to complete?

13. What actions are performed in the ROB-techniques after an instruction has completed?

14. What is the essence of the operand fetch policies?

15. When does the processor employ the split-register principle?

16. What is the function of rename buffers?

17. How to determine the maximal number of instructions that may have been issued but not yet completed in the processor (npmax)?

18. Why do a few high-performance processors implement two copies of particular register files?

19. What three components of the design space are related to register mapping?

20. What impedes realization of the maximal number of renames?

21. In what case can the renamed buffer be cleared?

22. In what cases do processors use mapping tables?

23. What is searched in all entries with the use of the associative lookup?

Questions for Self-Testing on Module III

1. What is a superscalar processor?

2. What is the SPARC architecture?

3. What is the IU register set?

4. What are register windows?

5. How to manage the register file?

6. How to use register windows?

7. What are the SPARC addressing modes?

8. What is the SPARC instruction set?

9. What are the general and call instruction formats?

10. What are the load and store instructions?

11. What are arithmetical and logical instructions?

12. What are the conditional branch instructions?

13. What is the floating-point on the SPARC?

14. What is the HyperSPARC II processor chips set ?

15. What is the UltraSPARC II system pipeline?

16. What is the power architecture?

17. What is the power-performance efficiency?

18. What is the base microarchitecture model?

19. What are the power-efficient microarchitecture design ideas and trends?

20. What are multicluster superscalar processors?

21. What is multithreading?

22. What are compiler support and energy-efficient cache architectures?

23. What is the microprocessor Power 3?

24. What is the microprocessor Power 4?

25. What are the microarchitecture level power-performance fundamentals?

26. What is the design space of register renaming techniques?

27. What is register renaming?

28. What is the scope of register renaming?

29. What are the register mapping methods?

30. What is the main feature of the NUMA architecture?

31. Why is the NUMA architecture considered as a hybrid architecture?

32. What is the condition for cache to be coherent?

33. What is the main peculiarity of the SMP architecture?

34. What class do conveyor systems belong to?

35. What is the bus scalability limited by?

36. What is the bus throughput limited by?

37. What architecture solutions is the SPARC system based on?

38. What is the role of software in scaling of computer systems?

39. What is the need in scaling of computer systems?