- •V. Ya. Krakovsky, m. B. Fesenko
- •In Computer Systems and Networks
- •Contents
- •Preface
- •Introduction
- •Module I. Basic Components of Digital Computers
- •1. The Structure of a Digital Computer
- •1.1. Introduction to Digital Computers
- •Questions for Self-Testing
- •1.2. The Computer Work Stages Implementation Sequence
- •Questions for Self-Testing
- •1.3. Register Gating and Timing of Data Transfers
- •Questions for Self-Testing
- •1.4. Computer Interface Organization
- •Questions for Self-Testing
- •1.5. Computer Control Organization
- •Questions for Self-Testing
- •1.6. Function and Construction of Computer Memory
- •Questions for Self-Testing
- •1.7. Architecturally-Structural Memory Organization Features
- •Questions for Self-Testing
- •2. Data processing fundamentals in digital computers
- •2.1. Element Base Development Influence on Data Processing
- •Questions for Self-Testing
- •2.2. Computer Arithmetic
- •Questions for Self-Testing
- •2.3. Operands Multiplication Operation
- •Questions for Self-Testing
- •2.4. Integer Division
- •Questions for Self-Testing
- •2.5. Floating-Point Numbers and Operations
- •Questions for Self-Testing
- •Questions for Self-Testing on Module I
- •Problems for Self-Testing on Module I
- •Module II. Digital computer organization
- •3. Processors, Memory, and the Evolution System of Instructions
- •3.1. Cisc and risc Microprocessors
- •Questions for Self-Testing
- •3.2. Pipelining
- •Questions for Self-Testing
- •3.3. Interrupts
- •Questions for Self-Testing
- •3.4. Superscalar Processing
- •Questions for Self-Testing
- •3.5. Designing Instruction Formats
- •Questions for Self-Testing
- •3.6. Building a Stack Frame
- •Questions for Self-Testing
- •4. The Structures of Digital Computers
- •4.1. Microprocessors, Microcontrollers, and Systems
- •Questions for Self-Testing
- •4.2. Stack Computers
- •Questions for Self-Testing
- •Questions for Self-Testing
- •4.4. Features of Organization Structure of the Pentium Processors
- •Questions for Self-Testing
- •4.5. Computers Systems on a Chip
- •Multicore Microprocessors.
- •Questions for Self-Testing
- •4.6. Principles of Constructing Reconfigurable Computing Systems
- •Questions for Self-Testing
- •4.7. Types of Digital Computers
- •Questions for Self-Testing
- •Questions for Self-Testing on Module II
- •Problems for Self-Testing on Module II
- •Module III. Parallelism and Scalability
- •5. Super Scalar Processors
- •5.1. The sparc Architecture
- •Questions for Self-Testing
- •5.2. Sparc Addressing Modes and Instruction Set
- •Questions for Self-Testing
- •5.3. Floating-Point on the sparc
- •Questions for Self-Testing
- •5.4. The sparc Computers Family
- •Questions for Self-Testing
- •6. Cluster Superscalar Processors
- •6.1. The Power Architecture
- •Questions for Self-Testing
- •6.2. Multithreading
- •Questions for Self-Testing
- •6.3. Power Microprocessors
- •Questions for Self-Testing
- •6.4. Microarchitecture Level Power-Performance Fundamentals
- •Questions for Self-Testing
- •6.5. The Design Space of Register Renaming Techniques
- •Questions for Self-Testing
- •Questions for Self-Testing on Module III
- •Problems for Self-Testing on Module III
- •Module IV. Explicitly Parallel Instruction Computing
- •7. The itanium processors
- •7.1. Parallel Instruction Computing and Instruction Level Parallelism
- •Questions for Self-Testing
- •7.2. Predication
- •Questions for Self-Testing
- •Questions for Self-Testing
- •7.4. The Itanium Processor Microarchitecture
- •Questions for Self-Testing
- •7.5. Deep Pipelining (10 stages)
- •Questions for Self-Testing
- •7.6. Efficient Instruction and Operand Delivery
- •Instruction bundles capable of full-bandwidth dispersal
- •Questions for Self-Testing
- •7.7. High ilp Execution Core
- •Questions for Self-Testing
- •7.8. The Itanium Organization
- •Implementation of cache hints
- •Questions for Self-Testing
- •7.9. Instruction-Level Parallelism
- •Questions for Self-Testing
- •7.10. Global Code Scheduler and Register Allocation
- •Questions for Self-Testing
- •8. Digital computers on the basic of vliw
- •Questions for Self-Testing
- •8.2. Synthesis of Parallelism and Scalability
- •Questions for Self-Testing
- •8.3. The majc Architecture
- •Questions for Self-Testing
- •8.4. Scit – Ukrainian Supercomputer Project
- •Questions for Self-Testing
- •8.5. Components of Cluster Supercomputer Architecture
- •Questions for Self-Testing
- •Questions for Self-Testing on Module IV
- •Problems for Self-Testing on Module IV
- •Conclusion
- •List of literature
- •Index and Used Abbreviations
- •03680. Київ-680, проспект Космонавта Комарова, 1.
Questions for Self-Testing
1. How may up-to-date computers be classified?
2. Why are parallel processing programs much harder to develop than sequential programs?
3. What is the essence of cluster computing systems?
4. What are the promising architecture decisions for MPP-systems?
5. How have the known architecture decisions influenced the computer evolution?
Questions for Self-Testing on Module II
1. What are CISC and RISC microprocessors?
2. What is CISC?
3. What is RISC?
4. What is the CDC 6600?
5. What is the IBM 801 project?
6. What are the Berkeley RISC and Stanford MIPS projects?
7. What is pipelining?
8. What does “one instruction per clock cycle” mean?
9. What are loads and the pipeline?
10. What is branching and branch delays?
11. What is the register structure of the CPU?
12. What is an interrupt?
13. What is an instruction format?
14. What are addressing modes?
15. What are procedure calls and the call instruction?
16. How to build a stack frame?
17. What is a precision architecture computer?
18. What is a FRISC?
19. What does “CISC + RISC = Pentium” mean?
20. What is the Pentium processor?
21. What is a pipeline and instruction flow?
22. What are the Pentium processor pipeline description and improvements?
23. What is branch prediction?
24. What is a floating point unit?
25. What are on-chip caches?
26. What is the Pentium processor bus designed for?
27. What is the Pentium Pro?
28. What types of digital computers do you know?
29. What new computer architectures do you know?
Problems for Self-Testing on Module II
1. Many instruction sets contain the instruction NOP, meaning no operation, which has no effect on the CPU state other than incrementing the program counter. Suggest some uses of this instruction.
2. Suppose a stack is to be used by the CPU to manage procedure calls and returns. Can the program counter be eliminated by using the top of the stack as a program counter?
3. Convert the following formulas from reverse Polish to infix:
a. AB + С + D
b. AB/CD/+
c. ABCDE + X X /
d. ABCDE + F/ + G - H/ X +
4. Convert the following formulas from reverse Polish to infix:
a. AB + С + D
b. AB/CD/+
c. ABCDE + X X /
d. ABCDE + F/ + G - H/ X +
5. Convert the expression A + В – С to postfix notation using Dijkstra's algorithm. Show the steps involved. Is the result equivalent to (A + B) – С or A + (B - C)? Does it matter?
6. How many times does the CPU need to refer to memory when it fetches and executes an indirect-address-mode instruction in the instruction is (a)a computation requiring a single operand; (b) a branch?
7. Is there any possible justification for an instruction with two opcodes?
8. Given the following memory values and a one-address machine with an accumulator, what values do the following instructions load into the accumulator?
– Word 20 contains 40.
– Word 30 contains 50.
– Word 40 contains 60.
– Word 50 contains 70.
– Word 60 contains 80.
a. LOAD IMMEDIATE 20
b. LOAD IMMEDIATE 20
c. LOAD IMMEDIATE 20
d. LOAD IMMEDIATE 30
e. LOAD IMMEDIATE 30
f. LOAD IMMEDIATE 30
9. a. If the last operation performed on a computer with an 8-bit word was an addition in which the two operands were 2 and 3, what would be the value of the following flags?
– Carry
– Zero
– Overflow
– Sign
– Even parity
– Half-carry
b. What if the operands were -1 (two’s complement) and +1?
10. When out-of-order complementation is used in a superscalar processor, resumption of execution after interrupt processing is complicated, because the exceptional condition may have been detected as an instruction that produced its result out of order. The program cannot be restarted at the instruction following the exceptional instruction, because subsequent instructions have already completed, and doing so would cause these instructions to be executed twice. Suggest a mechanism or mechanisms for dealing with this situation.
11. If the time slot of the computer is equal to 2 ns and it can perform 2 operations in each slot, what is the throughput of such a computer?
12. A conveyer consists of 5 stages. The times of operations of the stages are 1, 1, 2, 1, and 3 time slots accordingly. What is the maximal frequency of the results outputs if the data samples are input uninterruptedly?
13. Is the answer in the previous problem dependent on the order of the stages?
14. A computer contains 9 parallel-working devices; each of them can perform an operation during 9 time slots. What is the minimal time necessary for such computer to process 9 independent operations?
15. A conveyer consists of k stages, processing during n1, n2, nk time slots accordingly. What is the minimal slots number necessary for such a conveyer to perform m operations?