MINISTRY OF EDUCATION AND SCIENCE OF UKRAINE

National Aviation University

V. Ya. Krakovsky, m. B. Fesenko

DIGITAL COMPUTERS

Study Guide

Recommended by the Ministry of Education and Science

of Ukraine as a Study Guide for Students Specializing

In Computer Systems and Networks

Kyiv 2008

УДК 004.2 (075.8)

ББК з973.20-02я7

K81

Reviewed by: Prof. V. P. Boyun, Corresponding member of NAS of Ukraine, Dr. Sci. (Eng.), Head of the Department of Controlling Machines of Glushkov Institute of Cybernetics of NAS of Ukraine; Prof. G. M. Lutsky, Dr. Sci. (Eng.), Head of the Computer Engineering Department of National Technical University of Ukraine “Kyiv Polytechnic Institute” and two associate professors of this department: V. L. Selivanov, Cand. Sci. (Eng.), and A. M. Sergienko, Cand. Sci. (Eng.); and V. M. Yefimets, Cand. Sci. (Eng.), an associate professor of the Computer Systems and Networks Department of the State University of Information Communication Technologies of Ukraine

English language adviser O. Ye. Bugaiov

The Study Guide is concerned with the present-day situation in computer science and engineering which is a matter of interest for those who study the problems of design and application of computational digital machines.

The book is meant for students of the Institute of Computer Technologies, speciality 6.091500 “Computer Systems and Networks”.

Краковський В.Я.

K81	Цифрові ЕОМ: навч. посібник / В.Я. Краковський, М.Б. Фесенко.. – К.: НАУ, 2008. – 348 с. (Англ. мовою).

Рекомендовано Міністерством освіти і науки України як навчальний посібник для студентів вищих навчальних закладів, які навчаються за спеціальністю “Комп’ютерні системи та мережі” (лист № 14/18-Г-1293 від 4 червня 2008 року).

ISBN 978-966-598-501-3

Викладено сучасний стан світової обчислювальної техніки та питання проектування і використання цифрових ЕОМ.

Для студентів спеціальності 6.091500 “Комп’ютерні системи та мережі”.

УДК 004.2 (075.8)

ББК з973.20-02я7

ISBN 978-966-598-501-3

© Krakovsky V.Ya., Fesenko M.B., 2008

Contents

Preface 5

Introduction 6

Module I. Basic Components of Digital Computers 8

1. The Structure of a Digital Computer 8

1.1. Introduction to Digital Computers 8

1.2. The Computer Work Stages Implementation Sequence 11

1.3. Register Gating and Timing of Data Transfers 15

1.4. Computer Interface Organization 17

1.5. Computer Control Organization 22

1.6. Function and Construction of Computer Memory 28

1.7. Architecturally-Structural Memory Organization Features 38

2. Data Processing Fundamentals in Digital Computers 48

2.1 Element Base Development Influence on Data Processing 48

2.2. Computer Arithmetic 51

2.3. Operands Multiplication Operation 60

2.4. Integer Division 71

2.5. Floating-Point Numbers and Operations 74

Questions and Problems for Self-Testing on Module 1 82

Module II: Digital Computer Organization 89

3. Processors, Memory, and the Evolution System of Instructions 89

3.1. CISC and RISC Microprocessors 89

3.2. Pipelining 96

3.3. Interrupts 110

3.4. Superscalar Processing 120

3.5. Designing Instruction Formats 124

3.6. Building a Stack Frame 131

4. The Structures of Digital Computers 133

4.1. Microprocessors, Microcontrollers, and Systems 133

4.2. Stack Computers 137

4. 3. CISC + RISC = Pentium 146

4.4. Features of Organization Structure of the Pentium Processors 156

4.5. Computers Systems on a Chip 164

4.6. Principles of Constructing Reconfigurable Computing Systems 170

4.7. Types of Digital Computers 173

Questions and Problems for Self-Testing on Module 2 181

Module III: Parallelism and Scalability 184

5. Super Scalar Processors 184

5.1. The SPARC Architecture 184

5.2. SPARC Addressing Modes and Instruction Set 193

5.3. Floating-Point on the SPARC 201

5.4. The SPARC Computers Family 206

6. Cluster Superscalar Processors 214

6.1. The Power Architecture 214

6.2. Multithreading 221

6.3. Power Microprocessors 225

6.4. Microarchitecture Level Power-Performance Fundamentals 230

6.5. The Design Space of Register Renaming Techniques 236

Questions and Problems for Self-Testing on Module 3 251

Module IV: Expicitly Parallel Instruction Computing 254

7. The Itanium Processors 254

7.1. Parallel Instruction Computing and Instruction Level Parallelism 254

7.2. Predication 259

7.3. IA-64 Virtual Memory Model 265

7.4. The Itanium Processor Microarchitecture 268

7.5. Deep Pipelining (10 stages) 273

7.6. Efficient Instruction and Operand Delivery 279

7.7. High ILP Execution Core 283

7.8. The Itanium Organization 291

7.9. Instruction-Level Parallelism 298

7.10. Global Code Scheduler and Register Allocation 301

8. Digital computers on the Basic of VLIW 305

8.1. The 16-Way Itanium Server 305

8.2. Synthesis of Parallelism and Scalability 311

8.3. The MAJC Architecture 317

8.4. SCIT – Ukrainian Supercomputer Project 325

8.5. Components of Cluster Supercomputer Architecture 331

Questions and Problems for Self-Testing on Module 4 336

Conclusion 338

List of Literature 339

Index and Used Abbreviations 343