AT45DB642D
3. Block Diagram
WP |
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FLASH MEMORY ARRAY |
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PAGE (1024-/1056-BYTES) |
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BUFFER 1 (1024-/1056-BYTES) |
BUFFER 2 (1024-/1056-BYTES) |
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SCK/CLK |
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CS |
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I/O INTERFACE |
RESET |
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VCC |
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GND |
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RDY/BUSY |
SI |
SO |
I/O7 - I/O0 |
SER/BYTE |
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4. Memory Array
To provide optimal flexibility, the memory array of the AT45DB642D is divided into three levels of granularity comprising of sectors, blocks, and pages. The “Memory Architecture Diagram” illustrates the breakdown of each level and details the number of pages per sector and block. All program operations to the DataFlash occur on a page by page basis. The erase operations can be performed at the chip, sector, block or page level.
Figure 4-1. Memory Architecture Diagram
SECTOR ARCHITECTURE
SECTOR 0a = 8 Pages |
SECTOR 0 |
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8192/8,448 bytes |
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1 |
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SECTOR 0b = 248 Pages |
SECTOR |
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253,952/261,888 bytes |
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SECTOR 1 = 256 Pages |
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262,144/270,336 bytes |
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SECTOR 2 = 256 Pages |
2 |
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SECTOR |
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262,144/270,336 bytes |
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SECTOR 30 = 256 Pages |
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262,144/270,336 bytes |
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SECTOR 31 = 256 Pages |
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262,144/270,336 bytes |
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BLOCK ARCHITECTURE
BLOCK 0 |
8 Pages |
BLOCK 1
BLOCK 2
BLOCK 30
BLOCK 31
BLOCK 32
BLOCK 33
BLOCK 62
BLOCK 63
BLOCK 64
BLOCK 65
BLOCK 1022
BLOCK 1023
Block = 8,192-/8,448-bytes
BLOCK 1 BLOCK 0
PAGE ARCHITECTURE
PAGE 0
PAGE 1
PAGE 6
PAGE 7
PAGE 8
PAGE 9
PAGE 14
PAGE 15
PAGE 16
PAGE 17
PAGE 18
PAGE 8,190
PAGE 8,190
Page = 1,024-/1,056-bytes
5
3542M–DFLASH–11/2012