16. Power-on/Reset State
When power is first applied to the device, or when recovering from a reset condition, the device will default to Mode 3. In addition, the output pins (SO or I/O7 - I/O0) will be in a high impedance state, and a high-to-low transition on the CS pin will be required to start a valid instruction. The mode (Mode 3 or Mode 0) will be automatically selected on every falling edge of CS by sampling the inactive clock state.
16.1Initial Power-up/Reset Timing Restrictions
At power up, the device must not be selected until the supply voltage reaches the VCC (min.) and further delay of tVCSL. During power-up, the internal Power-on Reset circuitry keeps the device in reset mode until the VCC rises above the Power-on Reset threshold value (VPOR). At this time, all operations are disabled and the device does not respond to any commands. After power up is applied and the VCC is at the minimum operating voltage VCC (min.), the tVCSL delay is required before the device can be selected in order to perform a read operation.
Similarly, the tPUW delay is required after the VCC rises above the Power-on Reset threshold value (VPOR) before the device can perform a write (Program or Erase) operation. After initial power-up, the device will default in Standby mode.
Table 16-1. |
Initial Power-up/Reset Timing Restrictions |
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Symbol |
Parameter |
Min |
Typ |
Max |
Units |
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tVCSL |
VCC (min.) to Chip Select low |
50 |
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µs |
tPUW |
Power-Up Device Delay before Write |
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20 |
ms |
allowed |
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VPOR |
Power-ON Reset Voltage |
1.5 |
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2.5 |
V |
17. System Considerations
The RapidS serial interface is controlled by the clock SCK, serial input SI and chip select CS pins. The sequential 8-bit Rapid8 is controlled by the clock CLK, eight I/Os and chip select CS pins. These signals must rise and fall monotonically and be free from noise. Excessive noise or ringing on these pins can be misinterpreted as multiple edges and cause improper operation of the device. The PC board traces must be kept to a minimum distance or appropriately terminated to ensure proper operation. If necessary, decoupling capacitors can be added on these pins to provide filtering against noise glitches.
As system complexity continues to increase, voltage regulation is becoming more important. A key element of any voltage regulation scheme is its current sourcing capability. Like all Flash memories, the peak current for DataFlash occur during the programming and erase operation. The regulator needs to supply this peak current requirement. An under specified regulator can cause current starvation. Besides increasing system noise, current starvation during programming or erase can lead to improper operation and possible data corruption.
The device uses an adaptive algorithm during program and erase operations. In order to optimize the erase and program time, use the RDY/BUSY bit of the status register or the RDY/BUSY pin to determine whether the program or erase operation was completed. Fixed timing is not recommended.
32 AT45DB642D 
3542M–DFLASH–11/2012
AT45DB642D
18. Electrical Specifications
Table 18-1. Absolute Maximum Ratings*
Temperature under Bias |
................................ -55 C to +125 C |
*NOTICE: Stresses beyond those listed under “Absolute |
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Storage Temperature |
-65 C to +150 C |
Maximum Ratings” may cause permanent dam- |
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age to the device. The "Absolute Maximum Rat- |
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All Input Voltages (except VCC but including NC pins) |
ings" are stress ratings only and functional |
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operation of the device at these or any other con- |
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with Respect to Ground ................................... |
-0.6V to +6.25V |
ditions beyond those indicated in the operational |
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sections of this specification is not implied. Expo- |
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sure to absolute maximum rating conditions for |
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extended periods may affect device reliability. |
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All Output Voltages |
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Voltage Extremes referenced in the "Absolute |
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Maximum Ratings" are intended to accommo- |
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with Respect to Ground |
- 0.6V to VCC + 0.6V |
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date short duration undershoot/overshoot condi- |
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tions and does not imply or guarantee functional |
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device operation at these levels for any extended |
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period of time |
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Table 18-2. DC and AC Operating Range
|
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AT45DB642D |
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Operating Temperature (Case) |
Ind. |
-40 C to 85 C |
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VCC Power Supply |
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2.7V to 3.6V |
33
3542M–DFLASH–11/2012
Table 18-3. DC Characteristics
Symbol |
Parameter |
Condition |
Min |
Typ |
Max |
Units |
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= VIH, all inputs at |
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IDP |
Deep Power-down Current |
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CS, |
RESET, |
WP |
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15 |
25 |
µA |
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CMOS levels |
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= VIH, all inputs at |
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ISB |
Standby Current |
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CS, |
RESET, |
WP |
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25 |
50 |
µA |
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CMOS levels |
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(1) |
Active Current, Read Operation, |
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f = 33MHz; IOUT = 0mA; |
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10 |
15 |
mA |
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ICC1 |
Serial Interface |
VCC = 3.6V |
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(1) |
Active Current, Read Operation, |
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f = 33MHz; IOUT = 0mA; |
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10 |
15 |
mA |
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ICC2 |
Rapid8 Interface |
VCC = 3.6V |
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ICC3 |
Active Current, Program Operation, |
VCC = 3.6V |
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25 |
mA |
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Page Program |
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ICC4 |
Active Current, Page Erase, Block |
VCC = 3.6V |
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25 |
mA |
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Erase, Sector Erase Operation |
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ILI |
Input Load Current |
VIN = CMOS levels |
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1 |
µA |
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ILO |
Output Leakage Current |
VI/O = CMOS levels |
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1 |
µA |
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VIL |
Input Low Voltage |
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VCC x 0.3 |
V |
VIH |
Input High Voltage |
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VCC x 0.7 |
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V |
VOL |
Output Low Voltage |
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IOL = 1.6mA; VCC = 2.7V |
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0.4 |
V |
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VOH |
Output High Voltage |
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IOH = -100µA |
VCC - 0.2V |
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V |
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Notes: 1. AICC1 and ICC2 during a buffer read is 25mA maximum
2. All inputs (SI, SCK, CS#, WP#, and RESET#) are guaranteed by design to be 5-Volt tolerant
34 AT45DB642D 
3542M–DFLASH–11/2012
AT45DB642D
Table 18-4. AC Characteristics – RapidS/Serial Interface
Symbol |
|
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Parameter |
Min |
Typ |
Max |
Units |
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fSCK |
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SCK Frequency |
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66 |
MHz |
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fCAR1 |
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SCK Frequency for Continuous Array Read |
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66 |
MHz |
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fCAR2 |
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SCK Frequency for Continuous Array Read |
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33 |
MHz |
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(Low Frequency) |
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tWH |
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SCK High Time |
6.8 |
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ns |
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tWL |
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SCK Low Time |
6.8 |
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ns |
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(1) |
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SCK Rise Time, Peak-to-Peak (Slew Rate) |
0.1 |
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V/ns |
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tSCKR |
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(1) |
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SCK Fall Time, Peak-to-Peak (Slew Rate) |
0.1 |
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V/ns |
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tSCKF |
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tCS |
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Minimum |
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High Time |
50 |
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ns |
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CS |
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tCSS |
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Setup Time |
5 |
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ns |
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CS |
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tCSH |
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Hold Time |
5 |
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ns |
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CS |
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tCSB |
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CS |
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High to RDY/BUSY |
Low |
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100 |
ns |
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tSU |
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Data In Setup Time |
2 |
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ns |
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tH |
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Data In Hold Time |
3 |
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ns |
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tHO |
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Output Hold Time |
0 |
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ns |
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tDIS |
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Output Disable Time |
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27 |
35 |
ns |
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tV |
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Output Valid |
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6 |
ns |
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tWPE |
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Low to Protection Enabled |
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1 |
µs |
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WP |
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tWPD |
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High to Protection Disabled |
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1 |
µs |
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WP |
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tEDPD |
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High to Deep Power-down Mode |
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3 |
µs |
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CS |
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tRDPD |
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High to Standby Mode |
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35 |
µs |
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CS |
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tXFR |
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Page to Buffer Transfer Time |
|
|
400 |
µs |
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tcomp |
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Page to Buffer Compare Time |
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|
400 |
µs |
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tEP |
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Page Erase and Programming Time (1,024-/1,056-bytes) |
|
17 |
40 |
ms |
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tP |
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Page Programming Time (1,024-/1,056-bytes) |
|
3 |
6 |
ms |
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tPE |
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Page Erase Time (1,024-/1,056-bytes) |
|
15 |
35 |
ms |
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tBE |
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Block Erase Time (8,192-/8,448-bytes) |
|
45 |
100 |
ms |
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tSE |
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Sector Erase Time (262,144-/270,336-bytes) |
|
0.7 |
1.3 |
s |
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tCE |
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Chip Erase Time |
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TBD |
TBD |
s |
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tRST |
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Pulse Width |
10 |
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µs |
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RESET |
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tREC |
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Recovery Time |
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|
1 |
µs |
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RESET |
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Note: 1. |
Values are based on device characterization, not 100% tested in production |
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||||||||||
35
3542M–DFLASH–11/2012
Table 18-5. AC Characteristics – Rapid8 8-bit Interface
Symbol |
Parameter |
Min |
Typ |
Max |
Units |
fSCK1 |
|
CLK Frequency |
|
|
50 |
MHz |
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fCAR1 |
|
CLK Frequency for Continuous Array Read |
|
|
50 |
MHz |
|||||||
tWH |
|
CLK High Time |
9 |
|
|
ns |
|||||||
tWL |
|
CLK Low Time |
9 |
|
|
ns |
|||||||
(1) |
|
CLK Rise Time, Peak-to-Peak (Slew Rate) |
0.1 |
|
|
V/ns |
|||||||
tCLKR |
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|
|
||||||||||
(1) |
|
CLK Fall Time, Peak-to-Peak (Slew Rate) |
0.1 |
|
|
V/ns |
|||||||
tCLKF |
|
|
|
||||||||||
tCS |
|
Minimum |
|
High Time |
50 |
|
|
ns |
|||||
CS |
|
|
|||||||||||
tCSS |
|
|
|
Setup Time |
5 |
|
|
ns |
|||||
|
CS |
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tCSH |
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Hold Time |
5 |
|
|
ns |
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CS |
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tCSB |
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CS |
|
High to RDY/BUSY |
Low |
|
|
100 |
ns |
|||||
tSU |
|
Data In Setup Time |
2 |
|
|
ns |
|||||||
tH |
|
Data In Hold Time |
5 |
|
|
ns |
|||||||
tHO |
|
Output Hold Time |
0 |
|
|
ns |
|||||||
tDIS |
|
Output Disable Time |
|
|
12 |
ns |
|||||||
tV |
|
Output Valid |
|
|
12 |
ns |
|||||||
tWPE |
|
|
|
Low to Protection Enabled |
|
|
1 |
µs |
|||||
|
WP |
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|
||||||||||
tWPD |
|
|
|
High to Protection Disabled |
|
|
1 |
µs |
|||||
|
WP |
|
|
||||||||||
tEDPD |
|
|
High to Deep Power-down Mode |
|
|
3 |
µs |
||||||
|
CS |
|
|
||||||||||
tRDPD |
|
|
High to Standby Mode |
|
|
35 |
µs |
||||||
|
CS |
|
|
||||||||||
tXFR |
|
Page to Buffer Transfer Time |
|
|
400 |
µs |
|||||||
tcomp |
|
Page to Buffer Compare Time |
|
|
400 |
µs |
|||||||
tEP |
|
Page Erase and Programming Time (1,024-/1,056-bytes) |
|
17 |
40 |
ms |
|||||||
tP |
|
Page Programming Time (1,024-/1,056-bytes) |
|
3 |
6 |
ms |
|||||||
tPE |
|
Page Erase Time (1,024-/1,056-bytes) |
|
15 |
35 |
ms |
|||||||
tBE |
|
Block Erase Time (8,192-/8,448-bytes) |
|
45 |
100 |
ms |
|||||||
tSE |
|
Sector Erase Time (262,144-/270,336-bytes) |
|
1.6 |
5 |
s |
|||||||
tRST |
|
|
|
|
Pulse Width |
10 |
|
|
µs |
||||
|
RESET |
|
|
||||||||||
tREC |
|
|
|
|
Recovery Time |
|
|
1 |
µs |
||||
|
RESET |
|
|
||||||||||
Note: |
Values are based on device characterization, not 100% tested in production |
|
|
|
|||||||||
36 AT45DB642D 
3542M–DFLASH–11/2012