Лабораторная работа №3 / Laba_3 / Laba_3

// Netlist written 25 Октябрь 2005 г. 23:02:12 MSD
// By FastChip Version 2.6.0 Build 030604-1706
// Netlist last modified 25 Октябрь 2005 г. 23:02:09 MSD
netlist
module toplevel {
%%props;
unsourcedNets = "APPRST, SIN0, SIN1, FIQ, IRQ0, IRQ1, IRQ2, CTS, DSR, DCD, RI",
doesNotOutdateBinding (
MSSIU,
Timer_0,
Timer_1,
UART_0,
UART_1,
ICU,
Watchdog,
DMA,
Power,
Scratchpad,
Cache
),
moduleTouchTimes (
Cache = "0",
Clocks = "0",
CmdReg_A = "1130227745660",
DMA = "0",
ICU = "0",
lpm_and_A = "1130226341879",
lpm_inv_A = "1130266450187",
lpm_or_A = "1130266426250",
MCU = "0",
MSSIU = "0",
Output_A = "1130266469609",
Power = "0",
Scratchpad = "0",
Timer_0 = "0",
Timer_1 = "0",
UART_0 = "0",
UART_1 = "0",
Watchdog = "0"
)
%%end;
net CmdReg_A.clock;
net CmdReg_A.CMDREG_b11c12_decode0_rdsel;
net CmdReg_A.CMDREG_b11c12_decode0_wrsel;
net CmdReg_A.DMUX0_mnet;
net CmdReg_A.DMUX1_mnet;
net CmdReg_A.DMUX2_mnet;
net CmdReg_A.DMUX3_mnet;
net CmdReg_A.dw [3:0];
net CmdReg_A.rdsel;
net CmdReg_A.wrsel;
net DOR_DmuxSet_0_outNet;
net DOR_DmuxSet_1_outNet;
net DOR_DmuxSet_2_outNet;
net DOR_DmuxSet_3_outNet;
net notx [3:0];
net rez [3:0];
net x [3:0];
net x1;
net x2;
net y;
busclk CmdReg_A.bclk (.o=CmdReg_A.clock);
tselector CmdReg_A.CMDREG (.rdsel=CmdReg_A.rdsel, .wrsel=CmdReg_A.wrsel, :addrSource="allocated", :address="0x100ffffc", :isAutowait="false", :isExternal="false", :lane="LANEB0", :mask="0xffffffff", :physical="0x100ffffc", :size="0x1", :symbolic="reg");
tselector CmdReg_A.CMDREG_b11c12_decode0 (.rdsel=CmdReg_A.CMDREG_b11c12_decode0_rdsel, .wrsel=CmdReg_A.CMDREG_b11c12_decode0_wrsel, :addrSource="allocated", :address="0x100ffffc", :isAutowait="false", :isDuplicatedSelector="true", :isExternal="false", :lane="LANEB0", :mask="0xffffffff", :physical="0x100ffffc", :size="0x1", :symbolic="reg");
dataout CmdReg_A.DATAREAD0 (.i=DOR_DmuxSet_0_outNet, :bit="0");
dataout CmdReg_A.DATAREAD1 (.i=DOR_DmuxSet_1_outNet, :bit="1");
dataout CmdReg_A.DATAREAD2 (.i=DOR_DmuxSet_2_outNet, :bit="2");
dataout CmdReg_A.DATAREAD3 (.i=DOR_DmuxSet_3_outNet, :bit="3");
datain CmdReg_A.DATAWRITE0 (.o=CmdReg_A.dw[0], :bit="0");
datain CmdReg_A.DATAWRITE1 (.o=CmdReg_A.dw[1], :bit="1");
datain CmdReg_A.DATAWRITE2 (.o=CmdReg_A.dw[2], :bit="2");
datain CmdReg_A.DATAWRITE3 (.o=CmdReg_A.dw[3], :bit="3");
dff CmdReg_A.DFF0 (.ck=CmdReg_A.clock, .d=CmdReg_A.dw[0], .en=CmdReg_A.CMDREG_b11c12_decode0_wrsel, .q=x[3], :initv="1");
dff CmdReg_A.DFF1 (.ck=CmdReg_A.clock, .d=CmdReg_A.dw[1], .en=CmdReg_A.CMDREG_b11c12_decode0_wrsel, .q=x[2], :initv="0");
dff CmdReg_A.DFF2 (.ck=CmdReg_A.clock, .d=CmdReg_A.dw[2], .en=CmdReg_A.CMDREG_b11c12_decode0_wrsel, .q=x[1], :initv="1");
dff CmdReg_A.DFF3 (.ck=CmdReg_A.clock, .d=CmdReg_A.dw[3], .en=CmdReg_A.CMDREG_b11c12_decode0_wrsel, .q=x[0], :initv="0");
tdmux CmdReg_A.DMUX0 (.d=x[3], .de=null, .dw=null, .m=CmdReg_A.DMUX0_mnet, .me=null, .mw=null, .s=CmdReg_A.CMDREG_b11c12_decode0_rdsel, :DmuxBit="0", :DmuxGroup="DOR_DmuxSet_0_outNet_r9bc1", :DmuxSet="DOR_DmuxSet_0_outNet", :bit="0");
tdmux CmdReg_A.DMUX1 (.d=x[2], .de=null, .dw=null, .m=CmdReg_A.DMUX1_mnet, .me=null, .mw=null, .s=CmdReg_A.CMDREG_b11c12_decode0_rdsel, :DmuxBit="1", :DmuxGroup="DOR_DmuxSet_1_outNet_r9bc1", :DmuxSet="DOR_DmuxSet_1_outNet", :bit="1");
tdmux CmdReg_A.DMUX2 (.d=x[1], .de=null, .dw=null, .m=CmdReg_A.DMUX2_mnet, .me=null, .mw=null, .s=CmdReg_A.CMDREG_b11c12_decode0_rdsel, :DmuxBit="2", :DmuxGroup="DOR_DmuxSet_2_outNet_r10bc1", :DmuxSet="DOR_DmuxSet_2_outNet", :bit="2");
tdmux CmdReg_A.DMUX3 (.d=x[0], .de=null, .dw=null, .m=CmdReg_A.DMUX3_mnet, .me=null, .mw=null, .s=CmdReg_A.CMDREG_b11c12_decode0_rdsel, :DmuxBit="3", :DmuxGroup="DOR_DmuxSet_3_outNet_r10bc1", :DmuxSet="DOR_DmuxSet_3_outNet", :bit="3");
dor DOR_DmuxSet_0 (.i=CmdReg_A.DMUX0_mnet, .o=DOR_DmuxSet_0_outNet, :DmuxSet="DOR_DmuxSet_0_outNet");
dor DOR_DmuxSet_1 (.i=CmdReg_A.DMUX1_mnet, .o=DOR_DmuxSet_1_outNet, :DmuxSet="DOR_DmuxSet_1_outNet");
dor DOR_DmuxSet_2 (.i=CmdReg_A.DMUX2_mnet, .o=DOR_DmuxSet_2_outNet, :DmuxSet="DOR_DmuxSet_2_outNet");
dor DOR_DmuxSet_3 (.i=CmdReg_A.DMUX3_mnet, .o=DOR_DmuxSet_3_outNet, :DmuxSet="DOR_DmuxSet_3_outNet");
wide4 @(lpm_and_A:3,0) lpm_and_A.AND_WIDE4_0_0 (.ci=vcc, .co=rez[0], .i={vcc,x[0],notx[2],notx[3]}, :initv="#b1000_0000_0000_0000", :widefunc="AND");
wide4 @(lpm_and_A:2,0) lpm_and_A.AND_WIDE4_0_1 (.ci=vcc, .co=rez[1], .i={vcc,x[2],notx[1],x2}, :initv="#b1000_0000_0000_0000", :widefunc="AND");
wide4 @(lpm_and_A:1,0) lpm_and_A.AND_WIDE4_0_2 (.ci=vcc, .co=rez[2], .i={vcc,notx[1],x[2],x1}, :initv="#b1000_0000_0000_0000", :widefunc="AND");
wide4 @(lpm_and_A:0,0) lpm_and_A.AND_WIDE4_0_3 (.ci=vcc, .co=rez[3], .i={vcc,notx[0],notx[1],notx[3]}, :initv="#b1000_0000_0000_0000", :widefunc="AND");
lut4 lpm_inv_A.inv_1 (.i={null,null,null,x[0]}, .o=notx[0], :eq="~0");
lut4 lpm_inv_A.inv_2 (.i={null,null,null,x[1]}, .o=notx[1], :eq="~0");
lut4 lpm_inv_A.inv_3 (.i={null,null,null,x[2]}, .o=notx[2], :eq="~0");
lut4 lpm_inv_A.inv_4 (.i={null,null,null,x[3]}, .o=notx[3], :eq="~0");
wide4 @(lpm_or_A:0,0) lpm_or_A.AND_WIDE4_0_0 (.ci=gnd, .co=y, .i=rez[3:0], :initv="#b1111_1111_1111_1110", :widefunc="OR");
tpad Output_A.0 (.o=~y, .oe=vcc, :drive="WEAK", :isOutputLowPower="true", :slewRate="SLOW");
tpad Output_A.1 (.o=y, .oe=vcc, :drive="WEAK", :isOutputLowPower="true", :slewRate="SLOW");
}