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Figure 35: Typ. VDD - VOH @ VDD = 5 V (high sink ports)
Figure 36: Typ. VDD - VOH @ VDD = 3.3 V (high sink ports)
10.3.8Reset pin characteristics
Subject to general operating conditions for VDD and TA unless otherwise specified.
Table 42: NRST pin characteristics
|
Symbol |
Parameter |
Conditions |
Min |
Typ |
Max |
Unit |
|
VIL(NRST) |
NRST input low |
|
-0.3 |
- |
0.3 x VDD |
V |
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|
level voltage (1) |
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VIH(NRST) |
NRST input high |
IOL=2 mA |
0.7 x VDD |
- |
VDD + 0.3 |
|
|
|
level voltage (1) |
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VOL(NRST) |
NRST output low |
|
- |
- |
0.5 |
|
|
|
level voltage (1) |
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|
RPU(NRST) |
NRST pull-up |
|
30 |
55 |
80 |
kΩ |
|
|
resistor (2) |
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tIFP(NRST) |
NRST input filtered |
|
- |
- |
75 |
ns |
|
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pulse (3) |
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Symbol |
Parameter |
Conditions |
Min |
Typ |
Max |
Unit |
|
tINFP(NRST) |
NRST input not |
|
500 |
- |
- |
|
|
|
filtered pulse (3) |
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tOP(NRST) |
NRST output |
|
20 |
- |
- |
μs |
|
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pulse (3) |
|
15 |
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Notes:
(1)Data based on characterization results, not tested in production.
(2)The RPU pull-up equivalent resistor is based on a resistive transistor
(3)Data guaranteed by design, not tested in production.
Figure 37: Typical NRST VIL and VIH vs VDD @ 4 temperatures
Figure 38: Typical NRST pull-up resistance vs VDD @ 4 temperatures
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Figure 39: Typical NRST pull-up current vs VDD @ 4 temperatures
The reset network shown in the following figure protects the device against parasitic resets.
The user must ensure that the level on the NRST pin can go below VIL(NRST) max. (see Table 38: "I/O static characteristics" ), otherwise the reset is not taken into account
internally.
For power consumption sensitive applications, the external reset capacitor value can be reduced to limit the charge/discharge current. If NRST signal is used to reset external circuitry, attention must be taken to the charge/discharge time of the external capacitor to fulfill the external devices reset timing conditions. Minimum recommended capacity is 100 nF.
Figure 40: Recommended reset pin protection
10.3.9SPI serial peripheral interface
Unless otherwise specified, the parameters given in the following table are derived from tests performed under ambient temperature, fMASTER frequency and VDD supply voltage conditions. tMASTER = 1/fMASTER.
Refer to I/O port characteristics for more details on the input/output alternate function characteristics (NSS, SCK, MOSI, MISO).
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Table 43: SPI characteristics |
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Symbol |
Parameter |
Conditions |
Min |
Max |
Unit |
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fSCK1 |
SPI clock frequency |
Master mode |
0 |
8 |
MHz |
|
tc(SCK) |
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Slave mode |
0 |
6 |
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tr(SCK) |
SPI clock rise and fall |
Capacitive load: C = 30 |
|
25 |
ns |
|
tf(SCK) |
time |
pF |
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tsu(NSS)(1) |
NSS setup time |
Slave mode |
4 x |
|
ns |
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tMASTER |
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th(NSS)(1) |
NSS hold time |
Slave mode |
70 |
|
ns |
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tw(SCKH)(1) |
SCK high and low time |
Master mode |
tSCK/2 - 15 |
tSCK/2 + |
ns |
|
(1) |
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15 |
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tw(SCKL) |
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tsu(MI) (1) |
Data input setup time |
Master mode |
5 |
|
ns |
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tsu(SI)(1) |
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Data input setup time |
Slave mode |
5 |
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ns |
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th(MI) (1) |
Data input hold time |
Master mode |
7 |
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ns |
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th(SI)(1) |
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Data input hold time |
Slave mode |
10 |
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ns |
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ta(SO)(1)(2) |
Data output access time |
Slave mode |
|
3 x tMASTER |
ns |
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tdis(SO)(1)(3) |
Data output disable time |
Slave mode |
25 |
|
ns |
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tv(SO) (1) |
Data output valid time |
Slave mode |
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73 |
ns |
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(after enable edge) |
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tv(MO)(1) |
Data output valid time |
Master mode |
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36 |
ns |
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(after enable edge) |
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th(SO)(1) |
Data output hold time |
Slave mode |
28 |
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ns |
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(after enable edge) |
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th(MO)(1) |
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Master mode |
12 |
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ns |
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(after enable edge) |
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Notes:
(1)Values based on design simulation and/or characterization results, and not tested in production.
(2)Min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data.
(3)Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in Hi-Z.
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Figure 41: SPI timing diagram - slave mode and CPHA = 0
Figure 42: SPI timing diagram - slave mode and CPHA = 1(1)
1.Measurement points are made at CMOS levels: 0.3 VDD and 0.7 VDD.
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