35(/,0,1$5< 7(&+1,&$/ '$7$
ADSP-2196
For current information contact Analog Devices at 800/262-5643 |
September 2001 |
|
Host Port ACC Mode Write Cycle Timing
Table 15 and Figure 18 describe host port write operations in Address Cycle Control (ACC) mode. For more information on ACK, Ready, ALE, and ACC mode selection, see the Host port modes description on page 10.
Table 15. Host Port ACC Mode Write Cycle Timing
Parameter |
|
Description |
Min |
Max |
Unit |
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Switching Characteristics |
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tWHKS |
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asserted to HACK asserted (setup, ACK Mode) |
0.6 |
0.6+tNH1 |
ns |
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HWR |
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tWHKH |
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|
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de-asserted to HACK de-asserted (hold, ACK Mode) |
|
2 |
ns |
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HWR |
|
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tWHS |
|
|
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asserted to HACK asserted (setup, Ready Mode) |
|
0.6 |
ns |
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HWR |
|
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tWHH |
|
|
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asserted to HACK de-asserted (hold, Ready Mode) |
|
2+tNH1 |
ns |
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HWR |
|
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Timing Requirements |
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tWAL |
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asserted to HALE de-asserted (delay) |
1.5 |
|
ns |
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HWR |
|
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tCSAL |
|
|
|
or |
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|
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asserted to HALE asserted (delay) |
0 |
|
ns |
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HCMS |
HCIOMS |
|
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tALCS |
|
HALE de-asserted to optional |
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|
|
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or |
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|
|
1 |
|
ns |
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HCMS |
HCIOMS |
|
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|
|
de-asserted |
|
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tWCSW |
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|
de-asserted to |
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|
|
or |
|
|
|
|
de-asserted |
1 |
|
ns |
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HWR |
HCMS |
HCIOMS |
|
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tALW |
|
HALE asserted to HWR asserted |
0.5 |
|
ns |
|||||||||||||||||||||||||
tCSW |
|
|
or |
|
|
|
|
|
asserted to |
|
|
asserted |
1 |
2 |
ns |
|||||||||||||||
HCMS |
HCIOMS |
HWR |
||||||||||||||||||||||||||||
tWCS |
|
|
de-asserted (after last byte) to |
|
or |
1 |
|
ns |
||||||||||||||||||||||
HWR |
HCMS |
|
||||||||||||||||||||||||||||
|
|
HCIOMS |
de-asserted (ready for next write) |
|
|
|
||||||||||||||||||||||||
tALEW |
|
HALE de-asserted to HWR asserted |
1 |
|
ns |
|||||||||||||||||||||||||
tHKWD |
|
HACK asserted to |
|
|
|
de-asserted (hold, ACK Mode) |
1.5 |
|
ns |
|||||||||||||||||||||
HWR |
|
|||||||||||||||||||||||||||||
tADW |
|
Address valid to |
|
|
asserted (setup) |
4 |
|
ns |
||||||||||||||||||||||
HWR |
|
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tWAD |
|
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de-asserted to address invalid (hold) |
1 |
|
ns |
||||||||||||||||||||||||
HWR |
|
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tDWS |
|
Data valid to |
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de-asserted (setup) |
4 |
|
ns |
|||||||||||||||||||||||
HWR |
|
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tWDH |
|
|
de-asserted to data invalid (hold) |
1 |
|
ns |
||||||||||||||||||||||||
HWR |
|
|||||||||||||||||||||||||||||
1tNH are peripheral bus latencies (n tHCLK); these are internal DSP latencies related to the number of peripherals attempting to access DSP memory at the same time.
36 |
This information applies to a product under development. Its characteristics and specifications are subject to change with- |
REV. PrA |
|
out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. |
|
35(/,0,1$5< 7(&+1,&$/ '$7$
September 2001 |
For current information contact Analog Devices at 800/262-5643 |
|
ADSP-2196
+ & 0 6 |
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+ , 2 0 6 |
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W $ / & 6 |
W : & 6 : |
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W & 6 |
$ / |
W : $ / |
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+ $ / ( |
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W $ / : |
W & 6 : |
W : & 6 |
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W $ / ( : |
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+ : 5
W + . : '
W : + . 6 |
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W : + . + |
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+ $ & .
$ & . + $ & . ( $ & + % < 7 ( 0 2 ' (
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W : + + |
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W : + 6 |
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+ $ & . |
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5 ( $ ' < |
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+ $ & . ) ,5 6 7 % < 7 ( |
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0 2 ' ( |
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W ' : 6 |
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W $ ' : |
W : $ ' |
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W : ' + |
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+ $ ' ± |
$ ' ' 5 ( 6 6 |
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' $ 7 $ |
' $ 7 $ |
$ ' ' 5 ( 6 6 |
+ $ |
9 $ / ,' |
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9 $ / ,' |
9 $ / ,' |
9 $ / ,' |
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6 7 $ 5 7 |
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) , 5 6 7 |
/ $ 6 7 |
6 7 $ 5 7 |
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) , 5 6 7 : 2 5 ' |
% < 7 ( |
% < 7 ( |
1 ( ; 7 : 2 5 ' |
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||||
Figure 18. Host Port ACC Mode Write Cycle Timing
REV. PrA |
This information applies to a product under development. Its characteristics and specifications are subject to change with- |
37 |
|
out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. |
|
35(/,0,1$5< 7(&+1,&$/ '$7$
ADSP-2196
For current information contact Analog Devices at 800/262-5643 |
September 2001 |
|
Host Port ALE Mode Read Cycle Timing
Table 16 and Figure 19 describe host port read operations in Address Latch Enable (ALE) mode. For more information on ACK, Ready, ALE, and ACC mode selection, see the Host port modes description on page 10.
Table 16. Host Port ALE Mode Read Cycle Timing
Parameter |
|
Description |
Min |
Max |
Unit |
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Switching Characteristics |
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|
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|
|
|
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tRHKS |
|
|
|
asserted to HACK asserted (setup, ACK Mode) |
2 |
2+tNH1 |
ns |
||||||||||||||||||
HRD |
|||||||||||||||||||||||||
tRHKH |
|
|
|
de-asserted to HACK de-asserted (hold, ACK Mode) |
|
2 |
ns |
||||||||||||||||||
HRD |
|
||||||||||||||||||||||||
tRHS |
|
|
|
asserted to HACK asserted (setup, Ready Mode) |
|
2 |
ns |
||||||||||||||||||
HRD |
|
||||||||||||||||||||||||
tRHH |
|
|
|
asserted to HACK de-asserted (hold, Ready Mode) |
|
2+tNH1 |
ns |
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HRD |
|
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Timing Requirements |
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tCSAL |
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|
|
or |
|
|
|
asserted to HALE asserted (delay) |
0 |
|
ns |
|||||||||||||
HCMS |
HCIOMS |
|
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tALCS |
|
HALE de-asserted to optional |
|
|
|
or |
|
|
|
|
1 |
|
ns |
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HCMS |
HCIOMS |
|
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|
|
de-asserted |
|
|
|
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tRCSW |
|
|
|
de-asserted to |
|
|
|
|
or |
|
|
de-asserted |
1 |
|
ns |
||||||||||
HRD |
HCMS |
HCIOMS |
|
||||||||||||||||||||||
tALR |
|
HALE de-asserted to |
|
|
asserted |
1 |
|
ns |
|||||||||||||||||
HRD |
|
||||||||||||||||||||||||
tRCS |
|
|
de-asserted (after last byte) to |
|
or |
1 |
|
ns |
|||||||||||||||||
HRD |
HCMS |
|
|||||||||||||||||||||||
|
|
HCIOMS |
de-asserted (ready for next read) |
|
|
|
|||||||||||||||||||
tALPW |
|
HALE asserted pulsewidth |
4 |
|
ns |
||||||||||||||||||||
tHKRD |
|
HACK asserted to |
|
de-asserted (hold, ACK Mode) |
1.5 |
|
ns |
||||||||||||||||||
HRD |
|
||||||||||||||||||||||||
tAALS |
|
Address valid to HALE de-asserted (setup) |
4 |
|
ns |
||||||||||||||||||||
tALAH |
|
HALE de-asserted to address invalid (hold) |
1 |
|
ns |
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tRDH |
|
|
de-asserted to data invalid (hold) |
1 |
|
ns |
|||||||||||||||||||
HRD |
|
||||||||||||||||||||||||
1tNH are peripheral bus latencies (n tHCLK); these are internal DSP latencies related to the number of peripherals attempting to access DSP memory at the same time.
38 |
This information applies to a product under development. Its characteristics and specifications are subject to change with- |
REV. PrA |
|
out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. |
|
35(/,0,1$5< 7(&+1,&$/ '$7$
September 2001 |
For current information contact Analog Devices at 800/262-5643 |
|
ADSP-2196
+ & 0 6 + , 2 0 6
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$ / |
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+ $ / (
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W 5 & 6 |
+ 5 ' |
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+ $ & .
$ & . + $ & . ) 2 5 ( $ & + % < 7 ( 0 2 ' (
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W 5 + 6 |
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+$&. |
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5($'< |
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+ $ & . ) ,5 6 7 % < 7 ( |
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02'( |
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W $ $ / 6 |
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W $ / $ + |
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W 5 ' + |
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+ $ ' ± |
$ ' ' 5 ( 6 6 |
' $ 7 $ |
' $ 7 $ |
$ ' ' 5 ( 6 6 |
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9 $ / ,' |
9 $ / ,' |
9 $ / ,' |
9 $ / , ' |
+ $ |
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6 7 $ 5 7 |
) , 5 6 7 |
/ $ 6 7 |
6 7 $ 5 7 |
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) , 5 6 7 |
% < 7 ( |
% < 7 ( |
1 ( ; 7 : 2 5 ' |
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: 2 5 ' |
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Figure 19. Host Port ALE Mode Read Cycle TIming
REV. PrA |
This information applies to a product under development. Its characteristics and specifications are subject to change with- |
39 |
|
out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. |
|