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Аналіз обчислювальної похибки при виконанні базових операцій алгоритмів цифрової обробки сигналів. Обчислення математичних функцій роектування комп’ютерних засобів обробки сигналів та зображень Ваврук. Лаби для 13 групи / MAZ / MAZ-DOD-MAT-2012 / 214594697ADSP-2196M_pra.pdf

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35(/,0,1$5< 7(&+1,&$/ '$7$

ADSP-2196

For current information contact Analog Devices at 800/262-5643	September 2001

External Port Bus Request and Grant Cycle Timing

Table 13 and Figure 16 describe external port bus request and bus grant operations.

Table 13. External Port Bus Request and Grant Cycle Timing

Parameter

Description1, 2, 3

Min

Max

Unit

Switching Characteristics

tSD

CLKOUT high to

address, and

4.3

xMS,

RD/WR disable

tSE

CLKOUT low to

address, and

4.0

xMS,

RD/WR enable

tDBG

CLKOUT high to

asserted setup

2.2

tEBG

CLKOUT high to

de-asserted hold time

2.2

tDBH

CLKOUT high to

asserted setup

2.4

BGH

tEBH

CLKOUT high to

de-asserted hold time

2.4

BGH

Timing Requirements

tBS

asserted to CLKOUT high setup

4.6

tBH

CLKOUT high to

de-asserted hold time

0.0

1tHCLK is the peripheral clock period.

2These are preliminary timing parameters that are based on worst-case operating conditions.

3The pad loads for these timing parameters are 20 pF.

32	This information applies to a product under development. Its characteristics and specifications are subject to change with-	REV. PrA
	out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

35(/,0,1$5< 7(&+1,&$/ '$7$

September 2001	For current information contact Analog Devices at 800/262-5643

ADSP-2196

& / . 2 8 7

W % 6

W % +

% 5

W 6 '

W6 (

0 6 ±

,2 0 6

% 0 6

$ ±

W 6 '

W6 (

: 5

W 6 '

W6 (

5 '

W ' % *

W( % *

% *

% * +

W ' % +

W ( % +

Figure 16. External Port Bus Request and Grant Cycle Timing

REV. PrA	This information applies to a product under development. Its characteristics and specifications are subject to change with-	33
	out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

35(/,0,1$5< 7(&+1,&$/ '$7$

ADSP-2196

For current information contact Analog Devices at 800/262-5643	September 2001

Host Port ALE Mode Write Cycle Timing

Table 14 and Figure 17 describe host port write operations in Address Latch Enable (ALE) mode. For more information on ACK, Ready, ALE, and ACC mode selection, see the Host port modes description on page 10.

Table 14. Host Port ALE Mode Write Cycle Timing

Parameter

Description

Min

Max

Unit

Switching Characteristics

tWHKS

asserted to HACK asserted (setup, ACK Mode)

0.6

0.6+tNH1

HWR

tWHKH

de-asserted to HACK de-asserted (hold, ACK Mode)

HWR

tWHS

asserted to HACK asserted (setup, Ready Mode)

0.6

HWR

tWHH

asserted to HACK de-asserted (hold, Ready Mode)

2+tNH1

HWR

Timing Requirements

tCSAL

asserted to HALE asserted

HCMS

HCIOMS

tALPW

HALE asserted pulsewidth

tALCSW

HALE de-asserted to

de-asserted

HCMS

HCIOMS

tWCSW

de-asserted to

de-asserted

HWR

HCMS

HCIOMS

tALW

HALE de-asserted to

asserted

HWR

tWCS

de-asserted (after last byte) to

HWR

HCMS

de-asserted (ready for next write)

HCIOMS

tHKWD

HACK asserted to

de-asserted (hold, ACK Mode)

1.5

HWR

tAALS

Address valid to HALE de-asserted (setup)

tALAH

HALE de-asserted to address invalid (hold)

1.5

tDWS

Data valid to

de-asserted (setup)

HWR

tWDH

de-asserted to data invalid (hold)

HWR

1tNH are peripheral bus latencies (n tHCLK); these are internal DSP latencies related to the number of peripherals attempting to access DSP memory at the same time.

34	This information applies to a product under development. Its characteristics and specifications are subject to change with-	REV. PrA
	out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

35(/,0,1$5< 7(&+1,&$/ '$7$

September 2001	For current information contact Analog Devices at 800/262-5643

ADSP-2196

+ & 0 6
+ , 2 0 6
W & 6	$ /	W $ / 3 :	W $ / & 6 :		W : & 6 :
+ $ / (
			W $ / :			W : & 6
			W $ / :
+ : 5
				W + . : '
			W : + . 6		W : + . +
+ $ & .
$ & .						+ $ & . ( $ & + % < 7 (
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				W : + +
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+ $ & .
5 ( $ ' <						+ $ & . ) ,5 6 7 % < 7 (
						+ $ & . ) ,5 6 7 % < 7 (
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	W $ $ / 6		W $ / $ +		W : ' +
+ $ ' ±		$ ' ' 5 ( 6 6		' $ 7 $	' $ 7 $	$ ' ' 5 ( 6 6
		9 $ / ,'		9 $ / ,'	9 $ / ,'	9 $ / ,'
+ $
		6 7	$ 5 7	) , 5 6 7	/ $ 6 7	6 7 $ 5 7
		6 7	$ 5 7	) , 5 6 7	/ $ 6 7	1 ( ; 7 : 2 5 '
		) , 5 6 7 : 2 5 '		% < 7 (	% < 7 (	1 ( ; 7 : 2 5 '
		) , 5 6 7 : 2 5 '		% < 7 (	% < 7 (

Figure 17. Host Port ALE Mode Write Cycle Timing

REV. PrA	This information applies to a product under development. Its characteristics and specifications are subject to change with-	35
	out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

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