4Gb, 8Gb, and 16Gb x8 NAND Flash Memory
Timing Diagrams
Timing Diagrams
Figure 53: COMMAND LATCH Cycle
CLE
tCLS tCLH
tCS tCH
CE#
tWP
WE#
tALS tALH
ALE
tDS tDH
I/Ox |
COMMAND |
Don’t Care
Figure 54: ADDRESS LATCH Cycle
CLE |
|
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tCLS |
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tCS |
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CE# |
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tWC |
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tWP |
tWH |
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WE# |
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tALS |
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tALH |
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ALE |
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tDS tDH |
|
|
|
||
I/Ox |
Col |
Col |
Row |
Row |
Row |
|
add 1 |
add 2 |
add 1 |
add 2 |
add 3 |
||
|
||||||
Don’t Care |
Undefined |
PDF: 09005aef81b80e13/Source: 09005aef81b80eac |
65 |
Micron Technology, Inc., reserves the right to change products or specifications without notice. |
4gb_nand_m40a__2.fm - Rev. B 2/07 EN |
©2006 Micron Technology, Inc. All rights reserved. |
4Gb, 8Gb, and 16Gb x8 NAND Flash Memory
Timing Diagrams
Figure 55: INPUT DATA LATCH Cycle
CLE
|
|
|
tCLH |
CE# |
|
|
|
|
tALS |
|
tCH |
ALE |
|
|
|
|
tWC |
|
|
|
tWP |
tWP |
tWP |
WE# |
|
|
|
|
tWH |
|
|
|
tDS tDH |
tDS tDH |
tDS tDH |
I/Ox |
DIN 0 |
DIN 1 |
DIN Final1 |
Don’t Care
Notes: 1. DIN Final = 2,111 (x8).
Figure 56: SERIAL ACCESS Cycle After READ |
|
||
|
tCEA |
|
|
CE# |
|
|
|
|
tREA |
tREA |
tCHZ |
|
tREA |
||
|
tRP |
tREH |
tCOH |
RE# |
|
|
|
|
|
tRHZ |
tRHZ |
|
|
|
tRHOH |
I/Ox |
DOUT |
DOUT |
DOUT |
tRR |
tRC |
R/B#
Don’t Care
Note: |
Use this timing diagram for tRC ≥ 30ns. |
PDF: 09005aef81b80e13/Source: 09005aef81b80eac |
66 |
Micron Technology, Inc., reserves the right to change products or specifications without notice. |
4gb_nand_m40a__2.fm - Rev. B 2/07 EN |
©2006 Micron Technology, Inc. All rights reserved. |
4Gb, 8Gb, and 16Gb x8 NAND Flash Memory
Timing Diagrams
Figure 57: SERIAL ACCESS Cycle After READ (EDO Mode)
CE# |
|
|
|
tRC |
|
|
tCHZ |
tRP |
tREH |
|
tCOH |
RE# |
|
|
|
tREA |
tREA |
|
tRHZ |
tCEA |
tRLOH |
|
tRHOH |
I/Ox |
DOUT |
DOUT |
DOUT |
tRR
R/B#
Don’t Care
Note: |
Use this timing diagram for tRC < 30ns. |
Figure 58: READ STATUS Operation
|
|
|
tCLR |
|
|
CLE |
|
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tCLS |
tCLH |
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tCS |
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CE# |
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tWP |
tCH |
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WE# |
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tCEA |
tCHZ |
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||
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tWHR |
tRP |
tCOH |
RE# |
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tRHZ |
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tDS |
tDH |
tIR |
tREA |
tRHOH |
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|
||||
I/Ox |
70h |
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Status |
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|
output |
|||
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|
Don’t Care
PDF: 09005aef81b80e13/Source: 09005aef81b80eac |
67 |
Micron Technology, Inc., reserves the right to change products or specifications without notice. |
4gb_nand_m40a__2.fm - Rev. B 2/07 EN |
©2006 Micron Technology, Inc. All rights reserved. |
4Gb, 8Gb, and 16Gb x8 NAND Flash Memory
Timing Diagrams
Figure 59: TWO-PLANE/MULTIPLE-DIE READ STATUS Operation
tCS
CE# |
|
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tCLS |
tCLH |
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CLE |
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tWC |
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tWP |
tWP tWH |
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tCH |
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WE# |
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tCEA |
tCHZ |
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||
|
tALH |
tALS |
|
tALH |
tAR |
|
tCOH |
ALE |
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RE# |
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tRHZ |
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tDS |
tDH |
|
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tWHR |
tREA |
tRHOH |
I/Ox |
78h |
Row add 1 |
Row add 2 |
Row add 3 |
|
|
Status output |
Don’t Care
Figure 60: PAGE READ Operation
CLE
tCLR
CE#
tWC
WE#
tWB
tAR
ALE
|
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tR |
|
tRC |
tRHZ |
|
RE# |
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tRR |
|
tRP |
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I/Ox |
00h |
Col |
Col |
Row |
Row |
Row |
30h |
DOUT |
DOUT |
DOUT |
|
add 1 |
add 2 |
add 1 |
add 2 |
add 3 |
N |
N + 1 |
M |
||||
|
|
|
Busy
R/B#
Don’t Care
PDF: 09005aef81b80e13/Source: 09005aef81b80eac |
68 |
Micron Technology, Inc., reserves the right to change products or specifications without notice. |
4gb_nand_m40a__2.fm - Rev. B 2/07 EN |
©2006 Micron Technology, Inc. All rights reserved. |
4Gb, 8Gb, and 16Gb x8 NAND Flash Memory
Timing Diagrams
Figure 61: READ
Operation with CE# “Don’t Care”
CLE |
|
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|
CE# |
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|
RE# |
|
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ALE |
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tR |
|
R/B# |
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WE# |
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|
I/Ox |
00h |
Address (5 cycles) |
30h |
Data output |
|
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|
tCEA |
Don’t Care |
|
|
|
CE# |
|
|
|
|
tREA |
tCHZ |
|
|
|
RE# |
tCOH |
|
|
|
I/Ox |
Out |
Figure 62: RANDOM DATA READ Operation
CLE
|
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tCLR |
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CE# |
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WE# |
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tWB |
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tRHW |
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tAR |
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tWHR |
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||
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ALE |
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tR |
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tRC |
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tREA |
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RE# |
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tRR |
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I/Ox |
00h |
Col |
Col |
Row |
Row |
Row |
30h |
|
DOUT |
DOUT |
05h |
Col |
Col |
E0h |
DOUT |
DOUT |
|
|
add 1 |
add 2 |
add 1 |
add 2 |
add 3 |
|
|
N |
N + 1 |
|
add 1 |
add 2 |
|
M |
M + 1 |
|
|
Column address N |
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Column address M |
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||
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Busy |
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R/B# |
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Don’t Care |
|
PDF: 09005aef81b80e13/Source: 09005aef81b80eac |
69 |
Micron Technology, Inc., reserves the right to change products or specifications without notice. |
4gb_nand_m40a__2.fm - Rev. B 2/07 EN |
©2006 Micron Technology, Inc. All rights reserved. |
B .Rev - fm.2 m40a nand 4gb |
09005aef81b80e13/Source: PDF: |
EN 2/07 |
09005aef81b80eac |
70 |
|
All .Inc Technology, Micron ©2006 |
specifications or products change to right the reserves ,.Inc Technology, Micron |
.reserved rights |
.notice without |
Figure 63: PAGE READ CACHE MODE Operation, Part 1 of 2
CLE |
|
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|
tCLS tCLH |
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tCS |
tCH |
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CE# |
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tWC |
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WE# |
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tCEA |
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tRHW |
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ALE |
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tRC |
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RE# |
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tWB |
tR |
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||
tDS tDH |
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tREA |
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tRR |
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||
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I/Ox |
00h |
Col |
Col |
Row |
Row |
Row |
30h |
31h |
DOUT |
DOUT |
DOUT |
31h |
|
|
add 1 |
add 2 |
add 1 |
add 2 |
add 3 |
|
|
0 |
1 |
|
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|
|
Column address |
Page address |
|
|
tDCBSYR1 |
Page address |
|
||||
|
|
00h |
|
M |
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|
M |
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||
R/B# |
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Column address 0 |
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1 |
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Continued to |
1 |
|
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|
|
|
of next page |
|
|
DOUT |
|
0 |
tDCBSYR2 |
Page address |
M + 1 |
Column address 0
Don’t Care
Memory Flash NAND x8 16Gb and 8Gb, 4Gb, Diagrams Timing
B .Rev - fm.2 m40a nand 4gb |
09005aef81b80e13/Source: PDF: |
EN 2/07 |
09005aef81b80eac |
71 |
|
All .Inc Technology, Micron ©2006 |
specifications or products change to right the reserves ,.Inc Technology, Micron |
.reserved rights |
.notice without |
Figure 64: PAGE READ CACHE MODE Operation, Part 2 of 2
CLE
tCLS tCLH
tCS tCH
CE#
WE#
tCEA |
tRHW |
tRHW |
ALE
tRC
RE#
tWB
|
|
tRR |
|
|
|
|
|
|
|
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|
|
|
|
|
tDS tDH |
tREA |
|
|
|
|
|
|
|
|
|
|
|
I/Ox |
DOUT |
31h |
DOUT |
DOUT |
DOUT |
31h |
|
DOUT |
DOUT |
DOUT |
3Fh |
DOUT |
DOUT |
DOUT |
|
|
|
0 |
1 |
|
|
|
0 |
1 |
|
|
0 |
1 |
|
|
|
tDCBSYR2 |
Page address |
|
|
tDCBSYR2 |
Page address |
|
tDCBSYR2 |
Page address |
|
|||
|
|
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|
M + 1 |
|
|
|
|
M + 2 |
|
|
|
M + x |
|
R/B#
Column address 0 |
Column address 0 |
Column address 0 |
1 |
|
Don’t Care |
Continued from 1 of previous page
Memory Flash NAND x8 16Gb and 8Gb, 4Gb, Diagrams Timing
B .Rev - fm.2 m40a nand 4gb |
09005aef81b80e13/Source: PDF: |
EN 2/07 |
09005aef81b80eac |
72 |
|
All .Inc Technology, Micron ©2006 |
specifications or products change to right the reserves ,.Inc Technology, Micron |
.reserved rights |
.notice without |
Figure 65: PAGE READ CACHE MODE Operation without R/B#, Part 1 of 2
CLE |
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tCLS |
tCLH |
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tCS |
tCH |
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CE# |
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tWC |
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WE# |
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tCEA |
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tRHW |
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ALE |
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tRC |
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RE# |
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tDS tDH |
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tREA |
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||
I/Ox |
00h |
Col |
Col |
Row |
Row |
Row |
30h |
70h |
Status |
31h |
70h |
Status |
00h |
DOUT |
DOUT |
DOUT |
31h |
70h |
Status |
00h |
DOUT |
|
|
|
|
add 1 |
add 2 |
add 1 |
add 2 |
add 3 |
|
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|
0 |
1 |
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|
0 |
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|
Column address |
Page address |
|
I/O 5 = 0, Busy |
|
I/O 6 = 0, Cache busy |
|
Page address |
|
|
I/O 6 = 0, Cache busy |
Page address |
||||||||
|
|
|
00h |
|
|
M |
|
|
|
= 1, Ready |
|
|
= 1, Cache ready |
|
M |
|
|
|
= 1, Cache ready |
M + 1 |
||
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|
Column address 0 |
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Column address 0 |
|||
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1 |
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Continued to |
1 |
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Don’t Care |
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|
of next page |
|
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|
Memory Flash NAND x8 16Gb and 8Gb, 4Gb, Diagrams Timing
B .Rev - fm.2 m40a nand 4gb |
09005aef81b80e13/Source: PDF: |
EN 2/07 |
09005aef81b80eac |
73 |
|
All .Inc Technology, Micron ©2006 |
specifications or products change to right the reserves ,.Inc Technology, Micron |
.reserved rights |
.notice without |
Figure 66: PAGE READ CACHE MODE Operation without R/B#, Part 2 of 2
CLE
tCLS tCLH
tCS 
tCH
CE#
WE#
|
|
|
|
tCEA |
|
|
|
|
|
|
|
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|
tRHW |
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ALE |
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tRC |
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RE# |
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tDS tDH |
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tREA |
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|
|
I/Ox |
DOUT |
31h |
70h Status |
00h |
DOUT |
DOUT |
DOUT |
31h |
70h |
Status |
00h |
DOUT |
DOUT |
DOUT |
3Fh |
70h |
Status |
00h |
DOUT |
DOUT |
DOUT |
|
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|
0 |
1 |
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0 |
1 |
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0 |
1 |
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|
I/O 6 = 0, Cache busy |
|
Page address |
|
|
I/O 6 = 0, Cache busy |
|
Page address |
|
|
I/O 6 = 0, Cache busy |
|
Page address |
|
||||||
|
|
|
M + 1 |
|
|
|
M + 2 |
|
|
|
M + x |
|
|||||||||
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|
|
= 1, Cache ready |
|
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|
= 1, Cache ready |
|
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|
= 1, Cache ready |
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|
|||||
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|
Column address 0 |
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|
Column address 0 |
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|
Column address 0 |
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||||||
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1 |
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Don’t Care |
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Continued from |
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of previous page |
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Memory Flash NAND x8 16Gb and 8Gb, 4Gb, Diagrams Timing
4Gb, 8Gb, and 16Gb x8 NAND Flash Memory
Timing Diagrams
Figure 67: READ ID Operation
CLE |
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CE# |
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WE# |
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tAR |
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ALE |
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RE# |
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tWHR |
tREA |
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I/Ox |
90h |
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00h |
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Byte 0 |
Byte 1 |
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Byte 2 |
Byte 3 |
Byte 4 |
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Address, 1 cycle |
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Note: |
See Table 8 on page 25 for actual values. |
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Figure 68: PROGRAM PAGE Operation |
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CLE |
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CE# |
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tWC |
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tADL |
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WE# |
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tWB |
tPROG |
tWHR |
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ALE |
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RE# |
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I/Ox |
80h |
Col |
Col |
Row |
Row |
Row |
DIN |
DIN |
10h |
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70h |
Status |
add 1 |
add 2 |
add 1 |
add 2 |
add 3 |
N |
M |
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SERIAL DATA |
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1 up to m Byte |
PROGRAM |
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READ STATUS |
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INPUT command |
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serial input |
command |
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command |
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R/B# |
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x8 device: m = 2,112 bytes |
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Don’t Care
PDF: 09005aef81b80e13/Source: 09005aef81b80eac |
74 |
Micron Technology, Inc., reserves the right to change products or specifications without notice. |
4gb_nand_m40a__2.fm - Rev. B 2/07 EN |
©2006 Micron Technology, Inc. All rights reserved. |
4Gb, 8Gb, and 16Gb x8 NAND Flash Memory
Timing Diagrams
Figure 69: Program Operation with CE# “Don’t Care”
CLE
CE#
WE#
ALE |
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I/Ox |
80h |
Address (5 cycles) |
Data |
input |
Data |
input |
10h |
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tCS |
tCH |
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Don’t Care |
CE#
tWP
WE#
Figure 70: PROGRAM PAGE Operation with RANDOM DATA INPUT
CLE
CE#
tWC |
tADL |
tADL |
WE#
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tWB tPROG |
tWHR |
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ALE
RE#
I/Ox |
80h |
Col |
Col |
Row |
Row |
Row |
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add 1 |
add 2 |
add 1 |
add 2 |
add 3 |
SERIAL DATA
INPUT command
DIN |
DIN |
85h |
Col |
Col |
DIN |
DIN |
10h |
70h |
Status |
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N |
N+1 |
add 1 |
add 2 |
N |
N+1 |
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Serial input |
RANDOM DATA Column address |
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Serial input |
PROGRAM |
READ STATUS |
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INPUT command |
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command |
command |
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R/B#
Don’t Care
PDF: 09005aef81b80e13/Source: 09005aef81b80eac |
75 |
Micron Technology, Inc., reserves the right to change products or specifications without notice. |
4gb_nand_m40a__2.fm - Rev. B 2/07 EN |
©2006 Micron Technology, Inc. All rights reserved. |
4Gb, 8Gb, and 16Gb x8 NAND Flash Memory
Timing Diagrams
Figure 71: INTERNAL DATA MOVE Operation
CLE
CE#
tWC tADL
WE# |
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tWB |
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tWB tPROG |
tWHR |
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ALE |
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RE# |
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tR |
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I/Ox 00h |
Col |
Col |
Row |
Row |
Row |
35h |
85h |
Col |
Col |
Row |
Row |
Row |
Data |
Data |
10h |
70h |
Status |
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add 1 |
add 2 |
add 1 |
add 2 |
add 3 |
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add 1 |
add 2 |
add 1 |
add 2 |
add 3 |
1 |
N |
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READ |
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Busy |
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Busy |
STATUS |
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R/B# |
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INTERNAL |
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DATA MOVE |
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Don’t Care |
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Note: |
INTERNAL DATA MOVE operations are only supported within the plane from which data is |
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read. |
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Figure 72: PROGRAM PAGE CACHE MODE Operation
CLE
CE#
tWC |
tADL |
WE# |
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tWBtCBSY |
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tWBtLPROG |
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tWHR |
ALE |
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RE# |
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I/Ox |
80h |
Col |
Col |
Row |
Row |
Row |
DIN |
DIN |
15h |
80h |
Col |
Col |
Row |
Row |
Row |
DIN |
DIN |
10h |
70h |
Status |
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add 1 |
add 2 |
add 1 |
add 2 |
add 3 |
N |
M |
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add 1 |
add 2 |
add 1 |
add 2 |
add 3 |
N |
M |
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SERIAL DATA |
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Serial input PROGRAM |
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PROGRAM |
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INPUT |
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R/B# |
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Last page - 1 |
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Last page |
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Don’t Care
PDF: 09005aef81b80e13/Source: 09005aef81b80eac |
76 |
Micron Technology, Inc., reserves the right to change products or specifications without notice. |
4gb_nand_m40a__2.fm - Rev. B 2/07 EN |
©2006 Micron Technology, Inc. All rights reserved. |
B .Rev - fm.2 m40a nand 4gb |
09005aef81b80e13/Source: PDF: |
EN 2/07 |
09005aef81b80eac |
77 |
|
All .Inc Technology, Micron ©2006 |
specifications or products change to right the reserves ,.Inc Technology, Micron |
.reserved rights |
.notice without |
Figure 73: PROGRAM PAGE CACHE MODE Operation Ending on 15h
CLE
CE#
tWC
WE#
ALE
RE#
I/Ox 80h
SERIAL DATA
INPUT
tADL |
tADL |
Col |
Col |
Row |
Row |
Row |
DIN |
DIN |
15h |
70h |
Status |
80h |
Col |
Col |
Row |
Row |
Row |
DIN |
|
add 1 |
add 2 |
add 1 |
add 2 |
add 3 |
N |
M |
add 1 |
add 2 |
add 1 |
add 2 |
add 3 |
N |
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Serial input PROGRAM
Last page – 1 |
Last page |
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tWHR |
tWHR |
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DIN |
15h |
70h |
Status |
70h |
Status |
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M |
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PROGRAM |
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Poll status until: |
To verify successful completion of the last 2 pages: |
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I/O6 = 1, Ready |
I/O5 = |
1, Ready |
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I/O0 = 0, Last page PROGRAM successful |
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I/O1 = 0, Last page – 1 PROGRAM successful |
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Don’t Care
Memory Flash NAND x8 16Gb and 8Gb, 4Gb, Diagrams Timing
4Gb, 8Gb, and 16Gb x8 NAND Flash Memory
Timing Diagrams
Figure 74: BLOCK ERASE Operation
CLE
CE#
tWC
WE# |
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tWB |
tWHR |
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ALE |
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RE# |
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tBERS |
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I/Ox |
60h |
Row |
Row |
Row |
D0h |
70h |
Status |
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add 1 |
add 2 |
add 3 |
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Row address |
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ERASE |
READ STATUS |
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command |
command |
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Busy |
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R/B# |
AUTO BLOCK |
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I/O0 = |
0, Pass |
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ERASE SETUP |
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I/O0 |
= |
1, Fail |
Don’t Care |
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command |
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Figure 75: RESET Operation
CLE
CE#
tWB
WE#
tRST
R/B#
I/Ox |
FFh |
RESET command
PDF: 09005aef81b80e13/Source: 09005aef81b80eac |
78 |
Micron Technology, Inc., reserves the right to change products or specifications without notice. |
4gb_nand_m40a__2.fm - Rev. B 2/07 EN |
©2006 Micron Technology, Inc. All rights reserved. |