4Gb, 8Gb, and 16Gb x8 NAND Flash Memory
Command Definitions
RESET Operation
RESET FFh
The RESET command is used to put the memory device into a known condition and to abort the command sequence in progress.
READ, PROGRAM, and ERASE commands can be aborted while the device is in the busy state. The contents of the memory location being programmed or the block being erased are no longer valid. The data may be partially erased or programmed, and is invalid. The command register is cleared and is ready for the next command. The data register and cache register contents are marked invalid.
The status register contains the value E0h when WP# is HIGH; otherwise it is written with a 60h value. R/B# goes LOW for tRST after the RESET command is written to the command register (see Figure 47 and Table 10).
The RESET command must be issued to all CE#s after power-on. The device will be busy for a maximum of 1ms. Use of the TWO-PLANE/MULTIPLE-DIE READ STATUS (78h) command is prohibited during and following the initial RESET command and OTP operations.
Figure 47: RESET Operation
CLE |
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CE# |
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WE# |
tWB |
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tRST |
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R/B# |
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I/Ox |
FFh |
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RESET |
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command |
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Table 10: |
Status Register Contents After RESET Operation |
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Condition |
Status |
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Bit 7 |
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Bit 6 |
Bit 5 |
Bit 4 |
Bit 3 |
Bit 2 |
Bit 1 |
Bit 0 |
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WP# HIGH |
Ready |
1 |
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1 |
1 |
0 |
0 |
0 |
0 |
0 |
E0h |
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WP# LOW |
Ready and write protected |
0 |
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1 |
1 |
0 |
0 |
0 |
0 |
0 |
60h |
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PDF: 09005aef81b80e13/Source: 09005aef81b80eac |
56 |
Micron Technology, Inc., reserves the right to change products or specifications without notice. |
4gb_nand_m40a__2.fm - Rev. B 2/07 EN |
©2006 Micron Technology, Inc. All rights reserved. |
4Gb, 8Gb, and 16Gb x8 NAND Flash Memory
Command Definitions
WRITE PROTECT Operation
It is possible to enable and disable PROGRAM and ERASE commands using the WP# pin. Figures 48 through 51 illustrate the setup time (tWW) required from WP# toggling until a PROGRAM or ERASE command is latched into the command register. After command cycle 1 is latched, the WP# pin must not be toggled until the command is complete and the device is ready (status register bit 5 is “1”).
Figure 48: ERASE Enable
WE#
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tWW |
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I/Ox |
60h |
D0h |
WP#
R/B#
Figure 49: ERASE Disable
WE# |
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tWW |
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I/Ox |
60h |
D0h |
WP#
R/B#
Figure 50: PROGRAM Enable
WE# |
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tWW |
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I/Ox |
80h |
10h |
WP#
R/B#
PDF: 09005aef81b80e13/Source: 09005aef81b80eac |
57 |
Micron Technology, Inc., reserves the right to change products or specifications without notice. |
4gb_nand_m40a__2.fm - Rev. B 2/07 EN |
©2006 Micron Technology, Inc. All rights reserved. |