
- •Distinctive Characteristics
- •General Description
- •Ordering Information
- •Logic Diagram by Interface
- •Logic Diagram by Default Pin Function
- •Pin Connection Diagram—160-Pin PQFP Package
- •Pin and Signal Tables
- •Signal Descriptions
- •Table 4. Signal Descriptions
- •Architectural Overview
- •Detailed Description
- •Am186 Embedded CPU
- •Memory Organization
- •I/O Space
- •Serial Communications Support
- •Universal Serial Bus
- •Four HDLC Channels and Four TSAs
- •General Circuit Interface
- •Eight SmartDMA Channels
- •Two Asynchronous Serial Ports
- •Synchronous Serial Port
- •System Peripherals
- •Interrupt Controller
- •Four General-Purpose DMA Channels
- •48 Programmable I/O Signals
- •Three Programmable Timers
- •Hardware Watchdog Timer
- •Memory and Peripheral Interface
- •System Interfaces
- •Bus Interface Unit
- •Nonmultiplexed Address Bus
- •Byte Write Enables
- •Output Enable
- •DRAM Support
- •Chip Selects
- •Clock Control
- •In-Circuit Emulator Support
- •Clock Generation and Control
- •Features
- •System Clock
- •USB Clock
- •Clock Sharing by System and USB
- •Crystal-Driven Clock Source
- •Selecting a Crystal
- •External Clock Source
- •Static Operation
- •UART Baud Clock
- •Power Supply Operation
- •Power Supply Connections
- •Input/Output Circuitry
- •Operating Ranges
- •Maximum Load Derating
- •Power Supply Current
- •Table 9. Alphabetical Key to Switching Parameter Symbols
- •Table 10. Numerical Key to Switching Parameter Symbols
- •Table 23. DCE Interface Timing
- •Appendix A—Pin Tables
- •Table 27. Power-On Reset (POR) Pin Defaults
- •Table 28. Multiplexed Signal Trade-offs
- •Table 35. Pin List Summary
- •Related Documents
- •Customer Service
- •Hotline and World Wide Web Support
- •Corporate Applications Hotline
- •World Wide Web Home Page and FTP Site
- •Documentation and Literature
- •Literature Ordering

P R E L I M I N A R Y
and transceivers. The SSI supports data transfer speeds of up to 25 Mbit/s with a 50-MHz CPU clock.
The Am186CC SSI port operates as an interface master, with the other attached devices acting as slave devices. Using this protocol, the Am186CC controller sends a command byte to the attached device, and then follows that with either a read or write of a byte of data.
The SSI port consists of three I/O pins: an enable (SDEN), a clock (SCLK), and a bidirectional data pin (SDATA). SDEN can be used directly as an enable for a single attached device. When more than one device requires control via the SSI, PIOs can be used to provide enable pins for those devices.
The Am186CC SSI is mostly software compatible with software written for the Am186EM SSI. (Additional features have been added to the Am186CC SSI implementation.) In addition, the Am186CC controller features the additional capability of selecting the polarity of the SCLK and SDEN pins, as well as the shift order of bits on the SDATA pin (least-significant-bit first versus most-significant-bit first). The Am186CC SSI port also offers a programmable clock divisor (dividing the clock from 2 to 256 in power of 2 increments), a bidirectional transmit/receive shift register, and direct connection to AMD SLAC devices.
System Peripherals
Interrupt Controller
The Am186CC controller features an interrupt controller, which arranges the 36 maskable interrupt requests by priority and presents them one at a time to the CPU. In addition to interrupts managed by the interrupt controller, the Am186CC controller supports eight nonmaskable interrupts—an external or internal nonmaskable interrupt (NMI), a trace interrupt, and software interrupts and exceptions.
The Am186CC interrupt controller supports 36 maskable interrupt sources through the use of 15 channels. Because of this, most channels support multiple interrupt sources. These channels are programmable to support the external interrupt pins and/ or various peripheral devices that can be configured to generate interrupts. The 36 maskable interrupt sources include 19 internal sources and 17 external sources.
Four General-Purpose DMA Channels
The Am186CC controller provides a total of 12 DMA channels. Four of the channels are general purpose and can be used for data transfer between memory and I/O spaces (i.e., memory-to-I/O or I/O-to-memory) or within the same space (i.e., memory-to-memory or I/O-to-I/O). In addition, the Am186CC controller supports data transfer between peripherals and memory or I/O. On-chip peripherals that support gen era l - pur po se DM A ar e Tim er 2, the tw o
asynchronous serial ports (UART and High-Speed UART), and the USB controller. External peripherals support DMA transfers through the external DMA request pins. Each general-purpose channel accepts a DMA request from one of four sources: the DMA request pins (DRQ1–DRQ0), Timer 2, the UARTs, or the USB controller. In addition to the four generalpurpose channels, the Am186CC controller provides eight SmartDMA channels.
48 Programmable I/O Signals
The Am186CC contr oller provides 48 user - programmable input/output signals (PIOs). Each of these signals shares a pin with at least one alternate function. If an application does not need the alternate function, the associated PIO can be used by programming the PIO registers.
If a pin is enabled to function as a PIO signal, the alternate function is disabled and does not affect the pin. A PIO signal can be configured to operate as an input or output, with or without internal pullup or pulldown resistors (pullup or pulldown depends on the pin configuration and is not user-configurable), or as an open-drain output. Additionally, eight PIOs can be configured as external interrupt sources.
Three Programmable Timers
There are three 16-bit programmable timers in the Am186CC controller. Timers 0 and 1 are highly versatile and are each connected to two external pins (each one has an input and an output). These two timers can be used to count or time external events that drive the timer input pins. Timers 0 and 1 can also be used to generate nonrepetitive or variable-duty-cycle waveforms on the timer output pins.
Timer 2 is not connected to any external pins. It can be used by software to generate interrupts, or it can be polled for real-time coding and time-delay applications. Timer 2 can also be used as a prescaler to Timer 0 and Timer 1, or as a DMA request source.
The source clock for Timer 2 is one-fourth of the CPU clock frequency. The source clock for Timers 0 and 1 can be configured to be one-fourth of the CPU clock, or they can be driven from their respective timer input pins. When driven from a timer input pin, the timer is counting the “event” of an input transition.
The Am186CC controller also provides a pulse width demodulation (PWD) option so that a toggling input signal’s Low state and High state durations can be measured.
Hardware Watchdog Timer
The Am186CC controller provides a full-featured watchdog timer, which includes the ability to generate Non-Maskable Interrupts (NMIs), microcontroller resets, and system resets when the timeout value is
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Am186™CC Communications Controller Data Sheet |