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Пермский национальный исследовательский политехнический университет

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P R E L I M I N A R Y

LOGIC DIAGRAM BY INTERFACE

Reset/

Clocks

Address and

Address/Data

Buses

Bus Status and

Control

Programmable

Timers

Debug

Synchronous

Serial Interface

Asynchronous

Serial Interface

(UART)

High-Speed UART

UART Clock

Programmable I/O

(PIO)

Notes:

CLKOUT

INT8–INT0

RES

NMI

RESOUT

LCS

MCS3

–

MCS0

PCS7–PCS0

A19–A0

UCS

AD15–AD0

CAS0

ALE

CAS1

ARDY

RAS0

BHE

RAS1

BSIZE8

DEN

DCE_RXD_A, B, C, D

DCE_TXD_A, B, C, D

DRQ1–DRQ0

DCE_RCLK_A, B, C, D

DT/R

DCE_TCLK_A, B, C, D

HLDA

DCE_CTS_A, B, C, D

HOLD

DCE_RTR_A, B, C, D

S2–S0

PCM_RXD_A, B, C, D

PCM_TXD_A, B, C, D

SRDY

PCM_CLK_A, B, C, D

WHB

PCM_FSC_A, B, C, D

WLB

PCM_TSC_A, B, C, D

GCI_DD_A

PWD

GCI_DU_A

TMRIN1–TMRIN0

GCI_DCL_A

TMROUT1–TMROUT0

GCI_FSC_A

QS1–QS0

USBD+

USBD–

SDEN

USBSCI

SCLK

USBSOF

SDATA

USBX1

RXD_U

USBX2

TXD_U

UDMNS

CTS_U

UDPLS

RTR_U

UTXDMNS

UTXDPLS

RXD_HU

UXVOE

TXD_HU

UXVRCV

CTS_HU

RTR_HU

{ADEN}

{CLKSEL1}

UCLK

{CLKSEL2}

{ONCE}

PIO47–PIO0

{UCSX8}

{USBSEL1}

{USBSEL2}

{USBXCVR}

Interrupts

Chip

Selects

DRAM

Control

DCE Interface

(HDLC A–D)1

PCM Interface

(HDLC A–D)1

GCI Interface

(HDLC A)1

Universal Serial Bus (USB)

USB External

Transceiver

Interface

Configuration

Pinstraps

1.Because of multiplexing, not all interfaces are available at once. Refer to Table 28, “Multiplexed Signal Trade-offs,” on page 83.

6	Am186™CC Communications Controller Data Sheet

P R E L I M I N A R Y

LOGIC DIAGRAM BY DEFAULT PIN FUNCTION

Reset/

Clocks

Address and

Address/Data Buses

Bus Status and

Control

Debug

High-Speed UART

Chip

Selects

Universal Serial Bus

(USB)

Interrupts

No Connection

Notes:

CLKOUT

RES

RESOUT

DCE_RXD_A [GCI_DD_A] [PCM_RXD_A]

DCE_TXD_A [GCI_DU_A] [PCM_TXD_A]

DCE_RCLK_A [GCI_DCL_A] [PCM_CLK_A]

DCE_TCLK_A [GCI_FSC_A] [PCM_FSC_A]

A19–A0

AD15–AD0

PIO0 [TMRIN1]

ALE [PIO33]

PIO1 [TMROUT1]

ARDY [PIO8]

PIO2

[PCS5]

BHE [PIO34]

{ADEN}

PIO3 [PCS4]

{CLKSEL2}

BSIZE8

PIO4 [MCS0] {UCSX8}

DEN

[DS]

[PIO30]

PIO5

[MCS3]

[RAS1]

DRQ1

PIO6 [INT8] [PWD]

PIO7 [INT7]

DT/R [PIO29]

HLDA {CLKSEL1}

PIO8 [ARDY]

HOLD

PIO9 [DRQ0]

{USBXCVR}

PIO10 [SDEN]

PIO11 [SCLK]

PIO12 [SDATA]

SRDY [PIO35]

PIO17

PIO16 [RXD_HU]

WHB

[DCE_CTS_A] [PCM_TSC_A]

WLB

PIO18

[DCE_RTR_A]

WR [PIO15]

PIO19 [INT6]

PIO20 [TXD_U] [DCE_TXD_D] [PCM_TXD_D]

QS1–QS0

PIO21 [UCLK] [USBSOF] [USBSCI]

PIO22 [DCE_RCLK_C] [PCM_CLK_C]

TXD_HU

PIO23 [DCE_TCLK_C] [PCM_FSC_C]

PIO24

[CTS_U] [DCE_TCLK_D] [PCM_FSC_D]

LCS

PIO25

[RAS0]

[RTR_U] [DCE_RCLK_D] [PCM_CLK_D]

MCS1

[CAS1]

PIO26 [RXD_U] [DCE_RXD_D] [PCM_RXD_D]

MCS2

[CAS0]

PIO27 [TMRIN0]

PCS0 [PIO13] {USBSEL1}

PIO28 [TMROUT0]

PCS1 [PIO14] {USBSEL2}

PCS2

PIO31

[PCS7]

PCS3

PIO32

[PCS6]

UCS

{ONCE}

PIO36 [DCE_RXD_B] [PCM_RXD_B]

USBD+ [UDPLS]

PIO37 [DCE_TXD_B] [PCM_TXD_B]

USBD– [UDMNS]

PIO38

[DCE_CTS_B] [PCM_TSC_B]

USBX1

PIO39

[DCE_RTR_B]

USBX2

PIO40 [DCE_RCLK_B] [PCM_CLK_B]

PIO41 [DCE_TCLK_B] [PCM_FSC_B]

INT5–INT0

PIO42 [DCE_RXD_C] [PCM_RXD_C]

NMI

PIO43 [DCE_TXD_C] [PCM_TXD_C]

PIO44

[DCE_CTS_C] [PCM_TSC_C]

PIO45

[DCE_RTR_C]

PIO46

[CTS_HU]

[DCE_CTS_D] [PCM_TSC_D]

PIO47

[RTR_HU]

[DCE_RTR_D]

RSVRD1 [UXVRCV]

RSVRD2 [UXVOE]

RSVRD3 [UTXDMNS]

RSVRD4 [UTXDPLS]

HDLC A (DCE)

Programmable

I/O (PIO)

Pin names in bold indicate the default pin function. Brackets, [ ], indicate alternate, multiplexed functions. Braces, { }, indicate pinstrap pins.

Am186™CC Communications Controller Data Sheet

P R E L I M I N A R Y

PIN CONNECTION DIAGRAM—160-PIN PQFP PACKAGE

	V			TXDU/DCE TXD D/PCM TXD D	RXDU/DCE RXD D/PCM RXD D		CTSU/DCE TCLK D/PCM FSC D		RTRU/DCE RCLK D/PCM CLK D	V	DCETXD C/PCM TXD C	DCERXD C/PCM RXD C	DCECTS C/PCM TSC C		DCERTR C	DCERCLK C/PCM CLK C	DCETCLK C/PCM FSC C	V	INT8/PWD	INT7	INT6	TMRIN1	TMROUT1	TMRIN0	TMROUT0 V		DCETXD B/PCM TXD B	DCERXD B/PCM RXD B		DCECTS B/PCM TSC B		DCERTR B	DCERCLK B/PCM CLK B	DCETCLKB/PCM FSC B	V	UCS{ONCE}		LCS/RAS0	V	MCS3/RAS1	MCS2/CAS0		MCS1/CAS1		MCS0{UCSX8}	V		DRQ0		DCECTS A/PCM TSC A		DCERTR A		V






			CC							SS								CC								SS									CC				SS							CC								SS


	160			159	158		157	156		155	154	153	152	151		150	149	148	147	146	145	144	143	142	141	140	139	138	137		136		135	134	133	132	131		130	129	128	127		126		125		124		123	122			121

1			VSS																																																	VCC			120
2		SDEN																														DCE_TXD_A/GCI_DU_A/PCM_TXD_A																							119
3		SCLK																														DCE_RXD_A/GCI_DD_A/PCM_RXD_A																							118
4		SDATA																												DCE_RCLK_A/GCI_DCL_A/PCM_CLK_A																									117
5		PCS0 {USBSEL1}																												DCE_TCLK_A/GCI_FSC_A/PCM_FSC_A																									116
6			PCS1			{USBSEL2}																																														NMI			115
7			PCS2																																																RES				114
8		PCS3																																																	INT5				113
9		PCS4				{CLKSEL2}																																													INT4				112
10		PCS5																																																	INT3				111
11			PCS6																																																INT2				110
12		VCC																																																	INT1				109
13		PCS7																																																		VSS			108
14		ARDY																																																	INT0				107
15		SRDY																																																		VCC			106
16		WR																																																DRQ1					105
17			DT/R																																						RSRVD1/UXVRCV														104
18																																																							103
18			DEN/DS																																							RSRVD2/UXVOE													103
19		ALE																																						RSRVD3/UTXDMNS															102
20		BHE				{ADEN}																																		RSRVD4/UTXDPLS															101
21			VSS																																																	VSS			100
22		UCLK/USBSOF/USBSCI																																																HOLD					99
23																																									HLDA {CLKSEL1}														98
23		RTR_HU/DCE_RTR_D																																							HLDA {CLKSEL1}														98
24																																																							97
24		CTS_HU/DCE_CTS_D/PCM_TSC_D																																																			RD		97
25		RXD_HU																																																	WLB				96
26		TXD_HU																																																WHB					95
27		VCC																																															BSIZE8						94
28		AD0																																																AD15					93
29		AD8																																																		AD7			92
30		A0																																																		VCC			91
31		A1																																																		A19			90
32		A2																																																		A18			89
33		VSS																																																		A17			88
34		AD1																																																AD14					87
35		AD9																																																		AD6			86
36		A3																																																		A16			85
37		A4																																																		A15			84
38		AD2																																																		VSS			83
39		AD10																																													VSS_USB								82
40		VCC																																									USBD+/UDPLS												81

	41			42	43		44	45		46	47	48	49	50		51	52	53	54	55	56	57	58	59	60	61	62	63	64		65		66	67	68	69	70		71	72	73	74		75		76		77		78	79			80

	V			A5	A6		A7		A8	AD3	AD11	V	A9		A10	AD4	AD12	V	S6	S2	S1	{USBXCVR}S0	RESOUT	V	CLKOUT	V	QS0	QS1		A11		A12	AD5	AD13	VCC	A13		A14	V	V	X1		X2		USBX1	USBX2		V		V		V		/UDMNS-USBD
			SS									CC						SS						CC		SS													SS	SS								CC		CC USB
																																								A								A					CC
																																																					CC

8	Am186™CC Communications Controller Data Sheet

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