dsd1-10 / dsd-07=Verilog / Verilog-dsd19

// Verilog HDL for "DAC", "digital" "functional"

`timescale 1ns/10ps

module digital(CLK, Data, nEN, D, nEN_int) ;

input CLK, Data, nEN;

output [5:0] D;

output nEN_int;

reg [5:0] D, intern;

reg [2:0] counter;

reg nEN_int;

wire ready, next;

assign ready = (counter == 3'd6)?1: 0;

assign next = (counter == 3'd5)?1: 0;

always @(negedge CLK)

if(nEN_int) counter = 3'd0; else

if(ready) counter = 3'd0; else

counter = counter + 3'd1;

always @(posedge CLK)

if(next) D = intern;

always @(negedge CLK) nEN_int = nEN;

always @(posedge CLK)

if(next) intern = intern; else

intern = {intern[4],intern[3],intern[2],intern[1],Data,intern[0]};

endmodule

// Verilog HDL for "DAC", "digital" "verilog"

`timescale 1ns/10ps

// Generated by ac_shell v5.13-s022 on Fri Feb 25 10:04:34 MSK 2005.

// Restrictions concerning the use of Ambit BuildGates are covered in the

// license agreement. Distribution to third party EDA vendors is

// strictly prohibited.

module digital(CLK, Data, nEN, D, nEN_int);

input CLK;

input Data;

input nEN;

output [0:5] D;

output nEN_int;

wire [0:2] counter;

wire [0:5] intern;

NAND2X1 i_0(.A(counter[1]), .B(counter[0]), .Y(n_8));

MX2X1 i_1(.A(counter[0]), .B(n_18), .S0(counter[1]), .Y(n_9));

DFFX1 nEN_int_reg(.CK(n_114), .D(nEN), .Q(nEN_int), .QN(nEN_int_reg_inv)

);

SDFFSRX1 counter_reg_2(.CK(n_114), .D(1'b0), .Q(counter[2]), .QN(counter_reg_2_inv

), .RN(1'b1), .SE(n_8), .SI(n_16), .SN(1'b1));

SDFFSRX1 counter_reg_1(.CK(n_114), .D(n_17), .Q(counter[1]), .RN(1'b1),

.SE(counter[1]), .SI(\counter_1[0] ), .SN(1'b1));

SDFFSRX1 counter_reg_0(.CK(n_114), .D(1'b0), .Q(counter[0]), .QN(counter_reg_0_inv

), .RN(1'b1), .SE(n_9), .SI(nEN_int_reg_inv), .SN(1'b1));

SDFFSRX1 intern_reg_5(.CK(CLK), .D(intern[4]), .Q(intern[5]), .RN(1'b1),

.SE(n_10), .SI(intern[5]), .SN(1'b1));

SDFFSRX1 intern_reg_4(.CK(CLK), .D(intern[3]), .Q(intern[4]), .RN(1'b1),

.SE(n_10), .SI(intern[4]), .SN(1'b1));

SDFFSRX1 intern_reg_3(.CK(CLK), .D(intern[2]), .Q(intern[3]), .RN(1'b1),

.SE(n_10), .SI(intern[3]), .SN(1'b1));

SDFFSRX1 intern_reg_2(.CK(CLK), .D(intern[1]), .Q(intern[2]), .RN(1'b1),

.SE(n_10), .SI(intern[2]), .SN(1'b1));

AND2X1 i_2(.A(counter_reg_2_inv), .B(nEN_int_reg_inv), .Y(n_16));

SDFFSRX1 intern_reg_1(.CK(CLK), .D(intern[0]), .Q(intern[1]), .RN(1'b1),

.SE(n_10), .SI(intern[1]), .SN(1'b1));

AND2X1 i_5(.A(nEN_int_reg_inv), .B(counter[2]), .Y(n_17));

SDFFSRX1 intern_reg_0(.CK(CLK), .D(Data), .Q(intern[0]), .RN(1'b1), .SE(n_10

), .SI(intern[0]), .SN(1'b1));

AND2X1 i_9(.A(counter_reg_0_inv), .B(counter[2]), .Y(n_18));

SDFFSRX1 D_reg_5(.CK(CLK), .D(D[5]), .Q(D[5]), .RN(1'b1), .SE(n_10), .SI

(intern[5]), .SN(1'b1));

SDFFSRX1 D_reg_4(.CK(CLK), .D(D[4]), .Q(D[4]), .RN(1'b1), .SE(n_10), .SI

(intern[4]), .SN(1'b1));

AOI21X1 i_111(.A0(counter[0]), .A1(counter[1]), .B0(n_100), .Y(\counter_1[0]

));

SDFFSRX1 D_reg_3(.CK(CLK), .D(D[3]), .Q(D[3]), .RN(1'b1), .SE(n_10), .SI

(intern[3]), .SN(1'b1));

SDFFSRX1 D_reg_2(.CK(CLK), .D(D[2]), .Q(D[2]), .RN(1'b1), .SE(n_10), .SI

(intern[2]), .SN(1'b1));

NOR3X1 i_917(.A(counter[1]), .B(counter_reg_2_inv), .C(counter_reg_0_inv

), .Y(n_10));

SDFFSRX1 D_reg_1(.CK(CLK), .D(D[1]), .Q(D[1]), .RN(1'b1), .SE(n_10), .SI

(intern[1]), .SN(1'b1));

SDFFSRX1 D_reg_0(.CK(CLK), .D(D[0]), .Q(D[0]), .RN(1'b1), .SE(n_10), .SI

(intern[0]), .SN(1'b1));

INVX1 i_142(.A(n_16), .Y(n_100));

INVX1 i_143(.A(CLK), .Y(n_114));

endmodule