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Using the Value Change Link (VCL)

Using the Value Change Link (VCL)

The Toggle Test Application

This section serves two purposes:

It introduces the toggle test application that is used in “VCL Operations” on page 15 to illustrate certain aspects of a VCL application.

It uses the toggle test application to show how the activities that you must perform in a

VCL application are typically partitioned among the application’s routines.

Note: The code for the entire toggle test application can be found on all Verilog-XL release tapes in the following subdirectories:

tools/verilog/examples/PLI/toggle_count

tools/verilog/examples/PLI/toggle_test

What Is a Toggle Test?

A toggle test is an application that monitors a set of data elements in a design to determine if these elements have made transitions through a predefined set of states during simulation. When a data element has made a transition through this predefined set of states, it has toggled.

You run the toggle test application during a regular logic simulation. The resulting information gives you an upper bound (the highest percentage number you can count on) on fault detection/fault coverage for a particular set of vectors. You can use the information on nets that do not toggle to determine where there is little activity and pinpoint which regions of your design are not being exercised by the stimulus.

The fault coverage information from a toggle test is not deterministic. However, the toggle test application can be used to establish the effectiveness of a set of vectors in less time than it takes for a full fault simulation.

The Specification for This Implementation

The toggle test application is designed with the following specifications:

It can only be used with ASIC cell-based designs where the lower level modules are identified as cells within the Verilog description. Its basic functionality is to monitor the toggle information at the inputs and outputs of each cell instance.

January 2001

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Product Version 3.2

Using the Value Change Link (VCL)

Using the Value Change Link (VCL)

A toggle is defined as an occurrence of 1 to 0 and 0 to 1 transitions, where a transition from an x to 1 is equivalent to a transition from 0 to 1 and a transition from x to 0 is equivalent to a transition from 1 to 0.

It produces a report that indicates the percentage of cell ports and cell interconnect nets that have toggled.

The System Task Syntax

The toggle test will be implemented as a system task called $toggle_test. The syntax of the system task $toggle_test is as follows:

$toggle_test (module_instance1,module_instance2...);

The system task must be called with at least one module instance name. Each module instance argument specifies a hierarchical section of the design. The hierarchical section specifies where you want to perform the toggle test.

The following example illustrates a call to the $toggle_test system task in a Verilog module.

module top;

circuit m1(i1, i2, i3, o1, o2, o3);

//initiate toggle_test initial

$toggle_test(top.m1.a1, top.m1.a2.b4); // stimulus

.

.

.

endmodule

When you invoke the toggle test system task, the toggle test application hierarchically scans through the module instances in your file (see the Figure 1-1 on page 12 ). The scanning starts at each of the module instances you name in your system task call (in Figure 1-1 on page 12 , these are module instances a1 and b4). As the VCL application scans through the hierarchy, it searches for all of the cell instances in the hierarchies below the named module instances. (In the Figure 1-1 on page 12 the cell instances are cell1, cell2, cell3, cell5, and cell6.) When the VCL application finds a cell instance, the application initiates the toggle test at the input and output ports of the cell instance. In the Figure 1-3 on page 13 and Figure 1-3 on page 13 , the black dots indicate where the application initiates the toggle test.

By initiating the toggle test at the cell instances boundaries, the application monitors all of the wires that represent physical nets within a hierarchy.

January 2001

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Product Version 3.2

Using the Value Change Link (VCL)

Using the Value Change Link (VCL)

Figure 1-1 Hierarchical representation of a sample design

 

 

 

 

 

 

 

 

 

 

 

 

 

 

top

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

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a1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

a2

 

 

 

 

 

a3

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

b1

 

 

 

cell

 

 

cell

 

 

 

 

 

b4

 

 

 

cell

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

c1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

cell

 

c2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

cell

 

 

 

cell

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

cell

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Figure 1-2 Represents the module instance referred to as top.m1.a1

 

 

w1

 

 

 

 

 

 

 

 

w2

w3

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

cel11 cell2 cell3

c1

b1

a1

January 2001

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Product Version 3.2

Using the Value Change Link (VCL)

Using the Value Change Link (VCL)

Figure 1-3 Represents the module instance referred to as top.m1.a2.b4

cel16

cel15

c2

b4

The General Structure of the Application

The structure of the toggle test application is based on four major routines:

tg_check

tg_call

tg_misc

tg_process_toggle

The following table lists the actions that must be performed within the toggle test application and the pseudo-code for each of these routines.

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Product Version 3.2

Using the Value Change Link (VCL)

Using the Value Change Link (VCL)

Major toggle test routines

Routine and Actions

Pseudo-code

 

 

tg_check

start checktf routine

checks to see that the

check that at least one parameter is given

check that each parameter identifies a module

associated system task call

instance

is passed one or more

end checktf routine

parameters

 

checks that each parameter identifies a module instance

tg_call

start calltf routine

determines which nets need

for each monitored net

setup data structure for the net

monitoring

call acc_vcl_add to start monitoring the net

allocates and initializes the

end calltf routine

toggle test application data

 

structures

 

calls the VCL access routine acc_vcl_add for every net to be monitored

tg_misc

start misctf routine

supports save/restart

if save

process buffer

 

 

save data structure in save file

 

if restart

 

reallocate and initialize data structures

 

call acc_vcl_add to restart monitoring of all

 

nets that have not toggled

tg_process_toggle

stores VCL data into the buffer

processes the buffer if full

calls acc_vcl_delete to stop monitoring the net if the toggle test determines the net toggled successfully

start consumer routine

store the value change in the buffer if the buffer is full

for each value change in the buffer place into net data structure

if net toggled stop monitoring it reset

buffer

end consumer routine

January 2001

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Product Version 3.2

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