
- •Contents
- •Preface
- •Related Documents
- •Typographic and Syntax Conventions
- •Introduction to the Virtuoso XL Layout Editor
- •Editing Your Technology File for Virtuoso XL Layout Editor
- •Sample Technology File
- •Virtuoso XL Technology File Requirements
- •Layer Rules
- •Devices
- •Physical Rules
- •Virtuoso XL Rules (lxRules)
- •Compactor Rules
- •Preparing Your Connectivity Source for the Virtuoso XL Layout Editor
- •Placing Design Elements
- •Using Design Variables
- •Netlist Processor Expressions
- •Analog Expression Language Expressions
- •Simulation Design Variables
- •Using One-to-Many Mapping
- •Iterated Instances and Bus Pins
- •Multiplication Factor (mfactor)
- •Series-Connection Factor (sfactor)
- •One-to-Many Assignment with the Update Device Correspondence
- •Using Many-to-Many or Many-to-One Mapping
- •Modifying Many-to-Many or Many-to-One Mapping Between Components
- •Deleting Many-to-Many or Many-to-One Mapping Between Components
- •Using Virtuoso XL Properties
- •Using the lxUseCell Property to Specify Layout Devices to Use
- •Using the lvsIgnore Property to Exclude Schematic Symbols
- •Using the lxlgnoredParams Property to Exclude Device Properties
- •Using the lxRemoveDevice property to Ignore Parasitic Devices
- •Using the lxViewList and lxStopList Properties to Prepare Hierarchical Designs
- •Using the lxCombination Property to Build Complex Devices
- •Preparing Instances and Pins in Your Layout for the Virtuoso XL Layout Editor
- •Preparing Pins for the Virtuoso XL Layout Editor
- •Preparing Pins for Permutability
- •Search Order Variable
- •Syntax
- •Macros
- •Setting the permuteRule Property in the Symbol Master
- •Setting the permuteRule Property in the Device Master
- •Setting the permuteRule Property in the Symbol Instance
- •Setting the permuteRule Property in the Device Instance
- •Setting the permuteRule Property in the Component Description Format
- •Preparing Instances for Hierarchical Connectivity Checking
- •Setting Up Your Desktop
- •Customizing Your Desktop Layout
- •Using Multiple Cellviews
- •Printing to the Command Interpreter Window
- •Changing Display Colors
- •Using Bindkeys
- •Displaying Bindkeys
- •Loading Virtuoso XL Bindkeys
- •Setting Environment Variables
- •Information About Online Forms
- •Layout XL Options Form
- •Introduction to Abutment
- •Abutment Requirements
- •Setting Up Cells for Abutment
- •abutAccessDir
- •abutClass
- •Steps in Auto-Abutment
- •Sample Parameterized Cells Set Up for Abutment
- •Example 1
- •Example 2
- •Creating CMOS Pcells to Use with Abutment
- •autoAbutment Properties
- •The abutMosStretchMat Property
- •abutMosStretchMat Rules for MOS Abutment
- •Example Code Setting MOS Abutment Properties
- •Setting Environment Variables for Abutment
- •Move Together
- •Constraint Assisted
- •Using Device Abutment
- •Generating Your Layout with Virtuoso XL Layout Editor
- •Starting Virtuoso XL from the Schematic
- •Importing a Netlist for a Connectivity Reference
- •Starting Virtuoso XL from the Layout View
- •Connectivity Reference as a Netlist
- •Mapping File Structure
- •Working with Template Files
- •Saving Form Contents
- •Loading Template Files
- •Modifying Templates
- •Loading Template Files
- •Creating Template Files
- •Template File Syntax
- •General Syntax Rules
- •Boundaries Section
- •I/O Pins Section
- •Sample Template
- •Generating a Layout with Components Not Placed (Gen From Source)
- •Moving Components from the Schematic into the Layout (Pick from Schematic)
- •Placing a Group of Schematic Elements Together
- •Placing Individual Components
- •Generating Pins
- •Viewing Unplaced Instances/Pins
- •Viewing in Place
- •Manually Abutting Devices Using Pick from Schematic
- •Cloning Components
- •Cloning
- •Troubleshooting
- •Cloning Using Multiple Cellviews
- •Using Correspondence Points
- •Information About Online Forms
- •Add Correspondence Pairs Form
- •Cloning Form
- •Correspondence Pairs Form
- •Import XL Netlist Form
- •Layout Generation Options Form
- •Open File Form
- •Pick from Schematic Form
- •Remove Correspondence Components Form
- •Set Pin Label Text Style Form
- •Startup Option Form
- •Template File Form
- •Editing Your Layout with Virtuoso XL Layout Editor
- •Identifying Incomplete Nets
- •Moving Objects Manually in the Virtuoso XL Layout Editor
- •Moving Objects Using Move Options
- •Setting the Move Form to Appear Automatically
- •Aligning Objects
- •Post Selecting Devices
- •PreSelecting Devices
- •Swapping Components
- •Permuting Component Pins
- •Permuting Pins Manually
- •Checking Permutation Information
- •Using Device Locking
- •Using Automatic Spacing
- •Using Interactive Device Abutment
- •Setting Component Types
- •About Component Types
- •MOS Transistor Stacking and Folding Parameters
- •Modifying a Component Type
- •Using Transistor Chaining
- •Using Transistor Folding
- •Controlling the Folding Grid
- •Folding Transistors
- •Adding Instances to a Layout
- •Adding Pins to a Layout
- •Assigning Pins to a Net
- •Maintaining Connectivity When Editing a Flattened Pcell
- •Information About Online Forms
- •Assign Nets Form
- •Edit Component Types Form
- •Move Form
- •Set Transistor Folding Form
- •Show Incomplete Nets Form
- •Stretch Form
- •Virtuoso XL Alignment Form
- •Using the Virtuoso Custom Placer
- •Overview
- •Main Features
- •Place Menu Command Summary
- •Other Commands Used with the Virtuoso custom placer
- •Placement Styles
- •Setting Up the Virtuoso XL Layout Editor for Placement
- •Identifying the Placement Translation Rules
- •Setting Cadence Design Framework II Environment Variables
- •Setting Environment Variables for the Virtuoso Custom Router and Placer
- •Setting MOS Chaining and Folding Parameters
- •Abutting Standard Cells
- •Using Auto-Abutment During Placement
- •Placement Constraints
- •Constraint Manager Geometric Constraints
- •Pin Placement Constraints
- •Constraint Limitations
- •Placement Parameters and Component Types
- •MOS Transistor Chaining and Folding Parameters
- •Pin Placement
- •Assigning Pins to an Edge
- •Assigning Pins to a Fixed Position
- •Railing Pins
- •Loading the Template File
- •Assigning Spacing Between Pins
- •Saving Pin Placement to a Template File
- •Partitioning the Design
- •Creating a Partition
- •Loading the Template File
- •Saving Partitions to a Template File
- •Setting Placement Planning
- •Assisted CMOS Placement
- •Choose Component Types Form
- •Running the Virtuoso Custom Placer
- •Prerequisites to Placement
- •Running the Virtuoso Custom Placer: Initial Placement
- •Stopping the Placer
- •Running Load Balancing Service (LBS)
- •Troubleshooting Placement Results
- •Running the Virtuoso Custom Placer: Detailed Placement
- •Showing Congestions
- •Information About Forms
- •Auto Placer Form
- •Partitioning Form
- •Choose Component Types Form
- •Pin Placement Form
- •Load Template File Form
- •Placement Planning Form (Assisted CMOS)
- •Placement Planning Form (Assisted Standard Cell)
- •Placement Planning Form (Assisted Mixed CMOS/Standard-Cell)
- •Preparing Your Design for Routing in the Virtuoso XL Layout Editor
- •Understanding Connectivity
- •Pseudo-Parallel Connections
- •Selecting Layers
- •Changing Layers
- •Connecting Nets
- •Creating Paths
- •Connecting Nets with Path Stitching
- •Connecting Nets with Design Shapes
- •Checking Connectivity with Flight Lines
- •Checking Connectivity with Markers
- •Finding Markers
- •Explaining Markers
- •Deleting Single Markers
- •Deleting All Markers
- •Using the Virtuoso Compactor on a Routed Design
- •Overview
- •Main Features
- •Wire Editing Commands
- •Virtuoso Custom Router to Virtuoso XL Command Mapping
- •Prerequisites
- •Rule Information
- •Net Connectivity Information
- •Routing Area Boundary
- •Enabling Wire Editing
- •Toggling Between Virtuoso XL and Wire Editing Enabled
- •Loading ASCII Rules Files
- •The Wire Editing Environment
- •Status Banner
- •Preview Wires and Routing Aids
- •Mouse Button Behavior
- •Using Environment Variables
- •Routing Paths
- •Routing a Single Path
- •Routing Multiple Paths
- •Preventing and Checking Design Rule Violations
- •Interactive Checking
- •Same Net Checking
- •Checking Regions
- •Checking Route and Pin Violations
- •Routing Options and Styles
- •Matching Path Width and Pin Widths
- •Matching Path Width and Pin Widths for Multiple Paths
- •Gathering Bus Wires
- •Spacing for Gathered Bus Wires
- •Overriding Bus Spacing
- •Rotating the Bus Cursor
- •Cycling the Control Wire
- •Allowing Redundant Wiring
- •Allowing Orthogonal Jogs
- •Route To Cursor
- •Allow Floating Nets
- •Connecting Multiple Component Pins
- •Pushing Routes and Components
- •Routing Shielded Nets
- •Routing Tandem Layer Pairs
- •Using Vias
- •Changing Layers and Adding Vias
- •Using Vias Patterns on Multiple Paths
- •Legal Via Sites
- •Rotating Vias
- •Pseudo Vias
- •Editing Routed Connections
- •Stretching Paths and Vias
- •Splitting and Stretching Paths
- •Copying Routes
- •Using Critic Wire
- •Compacting Paths Using Pull
- •Displaying Reports
- •Displaying Routing Status Reports
- •Displaying Network Reports
- •Displaying Component Reports
- •Displaying Net Reports
- •Creating Rules Reports
- •Search Reports
- •Saving Reports
- •Setting Constraints
- •Using the Virtuoso Constraint Manager
- •Using .do Files
- •About the Forms
- •Add Via Form
- •Check Routes Form
- •Create Path Form
- •Find File Form
- •Layout
- •Reports Form
- •Route Options Form
- •Save As Form
- •Search Form
- •Split Form
- •Via Pattern Pop-up
- •Reports
- •Route Status Report Window
- •Network Report Window
- •Instance Report Window
- •Net Report Window
- •Rules Report Window
- •Setting Environment Variables
- •Troubleshooting
- •Finding Design Elements (Probing)
- •Probing Hierarchical Designs
- •Removing Probes
- •Exiting the Probe Command
- •Showing the Options Form
- •Checking Shorts and Opens
- •Comparing Design Elements and Parameters (Checking against the Connectivity Source)
- •Information About Online Forms
- •Probe Options Form
- •Updating Design Data in Virtuoso XL
- •Updating Layout Parameters
- •Updating Schematic Parameters
- •Updating Device Correspondence
- •Creating Device Correspondence
- •Needed Mode
- •Computer Aided Mode
- •Updating the Connectivity Reference
- •Changing the Device (Instance) View
- •Information About Online Forms
- •Change Instance View Form
- •Create Device Correspondence
- •Problems with the Interface
- •Invalid Markers from Previous Software Versions
- •Options Form Does Not Appear
- •Virtuoso XL Performance Is Slow
- •Problems with Editing
- •Components Move Slowly
- •Extra Probes Appear
- •Layout Generation Options Form Does Not Keep Values from the Last Entry
- •Parameters Not Updated
- •Schematic Not Editable
- •Warning to Update Your Design Appears at Startup
- •Problems with Connectivity
- •Connections Not Made
- •Incomplete Nets Command Does Not Recognize Connected Pins and Nets
- •Markers for Nonexistent Overlaps and Shorts Appear
- •Path Ends Not Accepted
- •Placement and Routing Do Not Run
- •Virtuoso XL Does Not Recognize Physical Vias
- •Moving Software Executables To a New Location
- •Environment Variables
- •Virtuoso XL Layout Editor
- •alignApplySeparation
- •alignApplySpacings
- •alignDirection
- •alignLayer
- •alignMethod
- •alignSelectionMode
- •alignSeparation
- •allowRotation
- •autoAbutment
- •autoArrange
- •autoPermutePins
- •autoSpace
- •checkTimeStamps
- •ciwWindow
- •compTypeRefLibs
- •constraintAssistedMode
- •createBoundaryLabel
- •crossSelect
- •extractEnable
- •extractStopLevel
- •globalPlacement
- •ignoredParams
- •ignoreNames
- •incNetCycleHilite
- •incNetHiliteLayer
- •infoWindow
- •initAspectRatio
- •initAspectRatioOption
- •initBoundaryLayer
- •initCreateBoundary
- •initCreateInstances
- •initCreateMTM
- •initCreatePins
- •initDoFolding
- •initDoStacking
- •initEstimateArea
- •initGlobalNetPins
- •initIOLabelType
- •initIOPinLayer
- •initIOPinName
- •initPinHeight
- •initPinMultiplicity
- •initPinWidth
- •initPrBoundaryH
- •initPrBoundaryW
- •initSymbolicPins
- •initUtilization
- •layoutWindow
- •lswWindow
- •lxAllowPseudoParallelNets
- •lxDeltaWidth
- •lxFingeringNames
- •lxGenerationOrientation
- •lxGenerationTopLevelOnly
- •lxInitResetSource
- •lxStackMinimalFolding
- •lxStackPartitionParameters
- •lxWidthTolerance
- •maintainConnections
- •mfactorNames
- •mfactorSplit
- •moveAsGroup
- •openWindow
- •optimizePlacement
- •paramTolerance
- •pathProbe
- •pathPurposeList
- •pathSwitchLayer
- •pathSwitchPurpose
- •preserveTerminalContacts
- •probeCycleHilite
- •probeDevice
- •probeHiliteLayer
- •probeInfoInCIW
- •probeNet
- •probePin
- •rowGroundLayer
- •rowGroundName
- •rowGroundWidth
- •rowPowerLayer
- •rowPowerName
- •rowPowerWidth
- •rowSupplyPosition
- •rowSupplySpacing
- •rowMOSSupplyPattern
- •rowSTDAllowFlip
- •rowSTDSupplyPattern
- •rulesFile
- •runTime
- •saveAs
- •saveAsCellName
- •saveAsLibName
- •saveAsViewName
- •schematicWindow
- •setPPConn
- •sfactorNames
- •sfactorParam
- •showIncNetEnable
- •stopList
- •templateFileName
- •traverseMixedHierarchies
- •updateReplacesMasters
- •updateWithMarkers
- •vcpConductorDepth
- •vcpKeepoutDepth
- •viewList
- •Wire Editor
- •allowFloatingNets
- •allowJogs
- •allowRedundantWiring
- •autoAdjustLength
- •autoShield
- •busOverride
- •busOverrideValue
- •busWireSpacing
- •busWireSpacingType
- •checkCornerCorner
- •checkCrosstalk
- •checkLength
- •checkLimitWay
- •checkMaxProcessWireWidth
- •checkMaxStackViaDepth
- •checkMaxTotalVia
- •checkMinMaskEdgeLength
- •checkMinProcessWireWidth
- •checkMiter
- •checkNetOrder
- •checkOffManGridPin
- •checkOffWireGridPin
- •checkPinSpacing
- •checkPolygonWire
- •checkProtected
- •checkReentrantPath
- •checkRegion
- •checkSameNet
- •checkSegment
- •checkStub
- •checkUseLayers
- •checkUseVias
- •checkWireExtension
- •doFile
- •enableBusRouting
- •enableTandemPair
- •gatherBusWires
- •inaccessiblePin
- •interactiveChecking
- •matchPinWidth
- •matchPinWidthValue
- •matchWireWidth
- •multiplePinsConnection
- •pinLargerMaxProcessWidth
- •pinSmallerMinProcessWidth
- •pushComponent
- •pushRouting
- •routeAsManyAsPossible
- •routeToCursor
- •routeToCursorStyle
- •sameNetChecking
- •showTimingMeter
- •showTimingOctagon
- •snapToPinOrigin
- •useDoFile
- •useRulesFile
- •viaAssistance
- •viaPattern
- •Private Environment Variables
- •Virtuoso XL Command Quick Reference
- •Using Spice and CDL For Netlist Driven Layout Generation
- •Introduction
- •Specifying Spice Designs
- •Cell Creation Rules
- •Character Considerations
- •Spice Statements
- •File Level Statements
- •Statements Allowed at File Level or within a Subckt Cell or a Top Level Cell
- •Statements Allowed within a Subckt Cell or a Top Level Cell
- •Spice Design Example
- •CDL Design Example
- •Parameter Resolution
- •Parameter Levels
- •Resolving Parameters
- •Putting the Rules Together (Examples)
- •Parameter Scaling
- •Complete ibuf Example Results
- •Virtuoso XL .do File Commands
- •Rule Hierarchy
- •circuit
- •Syntax
- •Example
- •Syntax
- •Example
- •limit
- •Syntax
- •Example
- •rule
- •Syntax
- •Example
- •Syntax

Virtuoso XL Layout Editor User Guide
Using the Virtuoso Custom Placer
Placement Planning Form (Assisted Standard Cell)
Partition lets you select a partition that was created from the Partitioning form.
Select From Layout allows you to select a partition from the layout window.
Style lets you select and load one of the available styles.
Assisted Standard Cell
Style File is used if you do not find the style you want to load then you can load a user defined style.
Browse opens the Open File form.
Load loads the file specified in the Style File field.
Load Row Template For activates the buttons and fields for the template file.
Entire Design loads the template for the entire design.
Selected Partition loads the template for the partition that you have selected.
Template File is the template file created from theDesign – Save To Template command.
Browse opens the Open File form.
Load loads the specified template file.
Region are used as boundaries within which to apply the parameters specified in the form. Once the rows are created the regions no longer exist, but you can still manipulate the rows. You can draw rows outside the region.
Region Shape determines the shape of the region.
Rectangle creates a rectangular region.
Origin X sets the X coordinate of the lower left corner of the lowest numbered row (region) being edited.
Origin Y sets the Y coordinate of the lower left corner of the row (region).
Width lets you enter the width of the row you want (larger than the height if you want horizontal rows).
Height lets you enter the height of the row you want (larger than the width if you want vertical rows).
Polygon creates a polygonal region.
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Using the Virtuoso Custom Placer
Points field appears after selecting the polygon option. Type in the coordinates, or when using the Draw option the points are updated in the Points text field.
Draw lets you use the mouse to specify the corners of a rectangle in the layout cellview.
The rectangle sets the placement region and the X, Y, Width, and Height fields are filled in with the appropriate values.
Update updates the region.
Delete removes the drawn region.
Properties are for the pins.
Allow For Pins secures a space from the boundary edge equal to the size of the pin plus the spacing rule. This prevents rows from overlapping pins.
Allow Region To Expand allows you to not decide on the size of the region. Therefore rows can grow beyond the chose region if they need to. The direction of growth is determined by the user.
Horizontally draw stretch rows in a horizontal direction.
Vertically draw stretch rows in a vertical direction.
Allow Partition To Expand applies the same concept to the partition boundary. Rows would be able to offshoot beyond the partition boundary.
Row allows you to create rows.
Row Name allows you to type a name for your row(s). If you do not specify a row name, the default row name is assigned, starting with Row1, Row2, etc.
Direction is the default direction for rows, either Vertical or Horizontal.
Utilization:
Within Row is how much of a row should be used by the components vs. how much should be left for routing. Specify either 100% Utilization or Specify %.
Between Row is how much of the region should be occupied by rows vs. how much should be left for routing channels. Specify the option Provide Row Spacing or
Specify %.
Number of Rows allows you to specify Maximum or Specify by typing in the text field the number of rows.
Standard Cell Grid is a user enforced grid.The value should not contradict the standard cell widths. The grid can be a fraction of the greatest common divisor of the standard cell widths.
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Virtuoso XL Layout Editor User Guide
Using the Virtuoso Custom Placer
For example if you have two cells of widths 2.5 and 4.5. The GCD is 0.5 so you can choose
0.01, 0.1, 0.5, etc.
Use Filler Cells
Use Substrate Contacts
Rails allows you to specify information for power and ground pins.
Power Rail
Layer allows you to specify the layout on which the rails are drawn.
Width allows you to specify the width of the supply rails.
Net Name allows you to specify the net to which the rows belong.
Ground Rail
Layer allows you to specify the layout on which the rails are drawn.
Width allows you to specify the width of the supply rails.
Net Name allows you to specify the net to which the rows belong.
Rail Pattern pattern and spacing to conform to the standard cell style. The patterns that you can use are GP, PG, GPPG, or PGGP.
Rail Spacing spacing between power and ground rails for the same row.
Layout Generation allows you to control whether components would have to be regenerated if necessary or only missing components would be added.
Regenerate All regenerates all components.
Generate Only Missing Components generates only missing components.
Preserve Constrained Objects is used with only the Regenerate All option. The constrained objects are not deleted.
Estimates creates the rows but does not generate any layout components.
Calculate Estimates gives you an estimation of the pmos and nmos devices within a row.
Update Layout updates the current layout with the assumption that you do not want to change any of the parameters.
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Virtuoso XL Layout Editor User Guide
Using the Virtuoso Custom Placer
Placement Planning Form (Assisted Mixed CMOS/Standard-Cell)
Partition lets you select a partition that was created from the Partitioning form.
Select From Layout allows you to select a partition from the layout window.
Style lets you select and load one of the available styles.
Assisted Standard Cell
Style File is used if you do not find the style you want to load then you can load a user defined style.
Browse opens the Open File form.
Load loads the file specified in the Style File field.
Load Row Template For activates the buttons and fields for the template file.
Entire Design loads the template for the entire design.
Selected Partition loads the template for the partition that you have selected.
Template File is the template file created from theDesign – Save To Template command.
Browse opens the Open File form.
Load loads the specified template file.
Region are used as boundaries within which to apply the parameters specified in the form. Once the rows are created the regions no longer exist, but you can still manipulate the rows. You can draw rows outside the region.
Region Shape determines the shape of the region.
Rectangle creates a rectangular region.
Origin X sets the X coordinate of the lower left corner of the lowest numbered row (region) being edited.
Origin Y sets the Y coordinate of the lower left corner of the row (region).
Width lets you enter the width of the row you want (larger than the height if you want horizontal rows).
Height lets you enter the height of the row you want (larger than the width if you want vertical rows).
Polygon creates a polygonal region.
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Using the Virtuoso Custom Placer
Points field appears after selecting the polygon option. Type in the coordinates, or when using the Draw option the points are updated in the Points text field.
Draw lets you use the mouse to specify the corners of a rectangle in the layout cellview.
The rectangle sets the placement region and the X, Y, Width, and Height fields are filled in with the appropriate values.
Update updates the region.
Delete removes the drawn region.
Properties are for the pins.
Allow For Pins secures a space from the boundary edge equal to the size of the pin plus the spacing rule. This prevents rows from overlapping pins.
Allow Region To Expand allows you to not decide on the size of the region. Therefore rows can grow beyond the chose region if they need to. The direction of growth is determined by the user.
Horizontally draw stretch rows in a horizontal direction.
Vertically draw stretch rows in a vertical direction.
Allow Partition To Expand applies the same concept to the partition boundary. Rows would be able to offshoot beyond the partition boundary.
Row allows you to create rows.
Row Name allows you to type a name for your row(s). If you do not specify a row name, the default row name is assigned, starting with Row1, Row2, etc.
Direction is the default direction for rows, either Vertical or Horizontal.
Utilization:
Within Row is how much of a row should be used by the components vs. how much should be left for routing. Specify either 100% Utilization or Specify %.
Between Row is how much of the region should be occupied by rows vs. how much should be left for routing channels. Specify the option Provide Row Spacing or
Specify %.
Number of Rows allows you to specify Maximum or Specify by typing in the text field the number of rows.
Standard Cell Grid
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Using the Virtuoso Custom Placer
Use Filler Cells allows you to enter the names of the Filler cells you defined in the Edit
Component Type form.
Use Substrate Contacts allows you to use the component types with a component class of STDSUBCONT.
Rails allows you to specify information for power and ground pins.
Power Rail
Layer allows you to specify the layout on which the rails are drawn.
Width allows you to specify the width of the supply rails.
Net Name allows you to specify the net to which the rows belong.
Ground Rail
Layer allows you to specify the layout on which the rails are drawn.
Width allows you to specify the width of the supply rails.
Net Name allows you to specify the net to which the rows belong.
Rail Pattern specifies how N and P devices alternate between rows or how PG and GP cells alternate. The patterns that you can use are GP, PG, GPPG, or PGGP.
Position controls the relative position of rails with regard to rows. Specify either Inside,
Outside, or Center.
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Row Spacing Within N-P Pair controls the distance between the N-P pair.
Minimum N-P Component specifies component spacing rule between N and P components.
Components
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PMOS
Width Threshold is the maximum width allowed after MOS device folding is performed. The default value comes from the CDF data for the device. If the threshold value is 0, the value of the Fold Threshold option set in the Edit
Component Types form is used.
Diffusion Spacing sets the minimum spacing required between adjacent MOS chains. This value affects the estimation of the number of rows required.
NMOS
Width Threshold is the maximum width allowed after MOS device folding is performed. The default value comes from the CDF data for the device.
Diffusion Spacing sets the minimum spacing required between adjacent MOS chains. This value affects the estimation of the number of rows required.
Align Components controls the relative alignment of devices in adjacent rows.
Inside aligns the P and N devices that are aligned toward each other.
Outside alignment aligns the devices away from each other.
Center aligns the devices with the row center line.
PMOS Offset to Row Edge is the distance between the edge of the devices that is closer to row edge and the edge of the row.
NMOS Offset To Row Edge is the distance between the edge of the devices that is closer to row edge and the edge of the row.
Allow Chaining determines that components will be chained.
Stack Partition Parameter sets the device stacking partition parameters.
Max Chain Size sets the maximum number of devices in stack.
Layout Generation allows you to control whether components would have to be regenerated if necessary or only missing components would be added.
Regenerate All regenerates all components.
Generate Only Missing Components generates only missing components.
Preserve Constrained Objects is used with only the Regenerate All option. The constrained objects are not deleted.
Estimates creates the rows but does not generate any layout components.
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Calculate Estimates gives you an estimation of the pmos and nmos devices within a row.
Update Layout updates the current layout with the assumption that you do not want to change any of the parameters.
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Placement Planning Form (Manual User-Defined)
Partition lets you select a partition that was created from the Partitioning form.
Select From Layout allows you to select a partition from the layout window.
Style lets you select and load one of the available styles.
Manual User-Defined
Style File is used if you do not find the style you want to load then you can load a user defined style.
Browse opens the Open File form.
Load loads the file specified in theStyle File field.
Load Row Template For activates the buttons and fields for the template file.
Entire Design loads the template for the entire design.
Selected Partition loads the template for the partition that you have selected.
Template File is the template file created from theDesign – Save To Template command.
Browse opens the Open File form.
Load loads the specified template file.
General
Row Name allows you to type a name for your row(s). If you do not specify a row name, the default row name is assigned, starting with Row1, Row2, etc.
Direction is the default direction for rows, either Vertical or Horizontal.
Initialize First Row
Draw lets you use the mouse to specify the corners of a rectangle in the layout cellview. The rectangle sets the placement region and the X, Y, Width, and Height
fields are filled in with the appropriate values.
Spacing Between Rows is how much of the region should be occupied by rows vs. how much should be left for routing channels.
Number of Rows to Create is the total number of rows in the list box.
Types
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Create allows you to change the options from Component Grid on down to create the component type.
Update allows you to select the component type in the Types field and change any of the attributes.
Edit opens the Choose Component Types form. Select an existing component type and click OK.
Component Type(s) the component type that you selected in the Choose Component Types form appears in this field.
Component Grid defines the component grid for the row(s).
Reference Point For Type allows you to set a reference point for a component type to be either Top, Center, Bottom, Origin.
Reference Point For Row allows you to set a reference point for a row to be either Top,
Center, or Bottom.
Type “Top” Offset From Row “Top” is the distance between the reference on the row and the reference on the component.
Allowed Orientations are R0, MY, R90, MXR90, MX, R180, MYR90, R270, AS IS
Rails
Rails allows you to create a user-defined rail using theLayer, Width, and Net Name options.
Add allows you to add the user-defined rail to theRails field.
Update allows you to update the Layer, Width, and Net Name for the selected rail.
Delete allows you to delete the selected rail.
Layer is the layer of the rail.
Width is the width of the rail.
Net Name is the name of the rail.
Reference Point For Rail allows you to set a reference point for the rail to be either
Top, Center, or Bottom.
Reference Point For Row allows you to set a reference point for a row to be either Top,
Center, or Bottom
Type “Top” Offset From Row “Top” is the distance between the reference on the row and the reference on the rail.
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Sort By allows you to sort the rows using different sorting filters which areName, Inc. X,
Inc. Y, Inc X, Dec. Y, Dec X, Inc Y, Dec. X, Dec. Y.
Number of Rows is the number of rows generated after running Calculate Estimates.
Search allows you to search for rows.
Choose From Layout allows you to select a row in the layout and have the row be highlighted in the list box.
Select All selects all rows in the list box.
Deselect All deselects all selected rows in the list box.
Create New creates new rows.
Update Selected changes any of the properties of the selected row that you have just changed.
Delete Selected allows you to delete any selected row.
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