Virtuoso XL Layout Editor User Guide

Checking Design Data in the Virtuoso XL Layout Editor

Finding Design Elements (Probing)

Probing lets you select a design element (component, net, or pin) in the layout (or schematic) window to highlight the corresponding element in the schematic (or layout) window.

To probe a design element, follow these steps.

1.From the layout window, choose Connectivity – XL Probe.

The layout window prompts you to point to a design object.

2.Click on a design object in the layout or schematic.

Virtuoso XL highlights the component, pin, or net you select in both the layout and the schematic (if both are open).

If you have multiple layout cellviews open, selecting a design element in one part of a cellview pair (a connectivity source and a layout) highlights the corresponding element in any other implementations of the other part.

For example, if you have several versions of a layout open, selecting R14 in the schematic highlights R14 in each of the layouts of that schematic.

If you want to use the Probe options, press F3.

Virtuoso XL Layout Editor User Guide

Checking Design Data in the Virtuoso XL Layout Editor

The Probe Options form appears. For more information about this form, see Information About Online Forms on page 453.

hilite layer

3.In the Object Filter section, turn on Pins, Nets, or Devices to choose the design elements to probe.

You can choose one, two, or all three of these design elements. When you click on a design element, the Probe Options form displays information about the selected device in the layout and schematic.

Virtuoso XL Layout Editor User Guide

Checking Design Data in the Virtuoso XL Layout Editor

For example, if you click on the Q12 device in the layout, Q12 is highlighted in both the schematic and the layout using the hilite color displayed in the Probe Options form

Display Layer box and the Probe Options form displays information about Q12.

dev:(lay)Q12->(sch)Q12

If you want this information to be displayed in the Command Interpreter Window (CIW), turn on Send Messages to CIW.

If you want to create a net class, so that you can probe nets in groups relevant to your design, select Tools-Constraint Manager. Change the Select Entity to Support Entities.

The form updates to display Classes.

You can also set the Show cyclic field to have the list box below display the names of all the pins, nets, net classes, or devices in the design. You can click on the names in the list box (instead of clicking on the objects in the design windows) to probe them.

To zoom in on the selected pins, nets, net classes, or devices in the list box, click the Zoom button.

Note: You can change the hilite drawing# layer colors from the Display Resources Editor.

4.To add additional elements to the Probe Information list, or to deselect items, hold down the Control key when you click on subsequent elements in the schematic, layout, or Probe form. You can select a range of names in the Probe Options form list by clicking on the top name and then clicking on the bottom name with Shift click.

If Virtuoso XL cannot find the design element in the schematic that corresponds to the one in the layout, you see a question mark (?) at the end of the listing in the form. The device might not exist in the schematic, or the schematic window might be iconified or closed.

dev:(lay)Q12->(sch)?

If you click on a place where there is more than one design element, Virtuoso XL highlights design elements in the following order:

1.Pins

2.Nets

3.Devices

Virtuoso XL Layout Editor User Guide

Checking Design Data in the Virtuoso XL Layout Editor

If you click on a place where there is more than one of the same kind of design element, a message window opens asking which one you want.

5. In the message window, click on the design element to probe and click OK.

Virtuoso XL highlights the component, net, or pin you choose and displays the information in the Virtuoso XL Probe Options form (if open).

Note: If you are cross-probing components bound by one-to-many/many-to-many/many-to- one mapping, probing one component bound by such mapping highlights all the components in the mapping group. If you probe an external net of a mapping group, the corresponding external net in the other window will be highlighted. Probing an internal net of a mapping group highlights the entire mapping group.

Note: If you open a schematic and two copies of the same layout, the Probe command applies to both layouts. If you have a schematic and two different layouts open, the Probe command applies to only the layout from which you selected the command.

Probing Hierarchical Designs

To probe a hierarchical design, follow these steps.

1.Open the layout and schematic (the cell view pair, pair #1) in Virtuoso XL.

2.Select the device to probe.

Virtuoso XL Layout Editor User Guide

Checking Design Data in the Virtuoso XL Layout Editor

In the diagram below, the device to probe is an inverter (CV1). It is represented in the layout as pair of transistors (a flat representation).

3.Choose Design – Hierarchy – Edit in Place.

The schematic of the inverter opens (CV3 in the diagram).

Virtuoso XL Cellview Pair #2)

If you select one of the transistors in this schematic to probe, the corresponding transistor in the layout in the level above is highlighted (CV2 in the diagram).

4.In the inverter schematic (CV3), select one of the two NMOS elements.

5.In the schematic window Tools menu, choose Design Synthesis – Layout XL to open the layout of the inverter (CV4 in the diagram) in Virtuoso XL.

Virtuoso XL Layout Editor User Guide

Checking Design Data in the Virtuoso XL Layout Editor

This creates another cellview pair (pair #2).

6.To descend into the schematic of the inverter, select one of the NMOS elements and from the schematic window choose Design – Hierarchy – Edit in Place.

Virtuoso XL Cellview Pair #2)

Virtuoso XL Cellview Pair #3)

The schematic of the NMOS opens (CV5 in the diagram).

If you probe the transistor in this schematic, the corresponding transistor in the layout in the level above is highlighted (CV4 in the diagram).

7.In the schematic window Tools menu, choose Design Synthesis – Layout XL to open the layout of the transistor (CV6 in the diagram) in Virtuoso XL.

This creates another cellview pair (pair # 3). You can probe from NMOS: Schematic back to Top: Layout, Inv: Layout, and NMOS: Layout