- •1 Summary of Features
- •2 General Device Information
- •2.1 Pin Configuration and Definition
- •3 Functional Description
- •3.1 Memory Subsystem and Organization
- •3.2 External Bus Controller
- •3.3 Central Processing Unit (CPU)
- •3.4 Interrupt System
- •3.6 Capture/Compare Unit (CAPCOM2)
- •3.7 Capture/Compare Units CCU6x
- •3.8 General Purpose Timer (GPT12E) Unit
- •3.9 Real Time Clock
- •3.10 A/D Converters
- •3.11 Universal Serial Interface Channel Modules (USIC)
- •3.12 MultiCAN Module
- •3.13 Watchdog Timer
- •3.14 Clock Generation
- •3.15 Parallel Ports
- •3.16 Instruction Set Summary
- •4 Electrical Parameters
- •4.1 General Parameters
- •4.2 DC Parameters
- •4.2.1 DC Parameters for Upper Voltage Area
- •4.2.2 DC Parameters for Lower Voltage Area
- •4.2.3 Power Consumption
- •4.3 Analog/Digital Converter Parameters
- •4.4 System Parameters
- •4.5 Flash Memory Parameters
- •4.6 AC Parameters
- •4.6.1 Testing Waveforms
- •4.6.2 Definition of Internal Timing
- •4.6.3 External Clock Input Parameters
- •4.6.4 External Bus Timing
- •4.6.5 Synchronous Serial Interface Timing
- •4.6.6 JTAG Interface Timing
- •5 Package and Reliability
- •5.1 Packaging
- •5.2 Thermal Considerations
XE167x
XE166 Family Derivatives
Package and Reliability
5 Package and Reliability
In addition to the electrical parameters, the following specifcations ensure proper integration of the XE167 into the target system.
5.1Packaging
These parameters specify the packaging rather than the silicon.
Table 36 |
Package Parameters (PG-LQFP-144-4) |
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Parameter |
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Symbol |
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Limit Values |
Unit |
Notes |
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Min. |
|
Max. |
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||
Exposed Pad Dimension |
Ex × Ey |
– |
|
6.5 × 6.5 |
mm |
– |
||
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Power Dissipation |
PDISS |
– |
|
1.0 |
W |
– |
||
Thermal resistance |
RΘJA |
– |
|
45 |
K/W |
No thermal via1) |
||
Junction-Ambient |
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36 |
K/W |
4-layer, no pad2) |
||
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|
22 |
K/W |
4-layer, pad3) |
1)Device mounted on a 2-layer JEDEC board (according to JESD 51-3) or a 4-layer board without thermal vias; exposed pad not soldered.
2)Device mounted on a 4-layer JEDEC board (according to JESD 51-7) with thermal vias; exposed pad not soldered.
3)Device mounted on a 4-layer JEDEC board (according to JESD 51-7) with thermal vias; exposed pad soldered to the board.
Data Sheet |
117 |
V2.1, 2008-08 |
XE167x
XE166 Family Derivatives
Package and Reliability
Package Outlines
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±0.05 |
±0.05 |
MAX. |
H |
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0.1 |
1.4 |
1.6 |
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0.5 |
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17.5 |
C |
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0.08 |
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0.22 ±0.05 |
2) |
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0.08 M A-B D C 144x |
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22 |
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0.2 A-B D 144x |
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20 1) |
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0.2 A-B D H 4x |
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D |
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A |
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B |
1) |
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20 |
22 |
Ey |
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144
1
+0.08 -0.03 |
7˚ MAX. |
0.12 |
|
0.6 ±0.15 |
|
Bottom View
Ex
Exposed Pad
144
1
Index Marking |
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|
1) |
Does not include plastic or metal protrusion of 0.25 max. per side |
|
2) |
Does not include dambar protrusion of 0.08 max. per side |
GPP01178 |
Figure 30 PG-LQFP-144-4 (Plastic Green Thin Quad Flat Package)
All dimensions in mm.
You can find complete information about Infineon packages, packing and marking in our Infineon Internet Page “Packages”: http://www.infineon.com/packages
Data Sheet |
118 |
V2.1, 2008-08 |
XE167x
XE166 Family Derivatives
Package and Reliability
5.2Thermal Considerations
When operating the XE167 in a system, the total heat generated in the chip must be dissipated to the ambient environment to prevent overheating and the resulting thermal damage.
The maximum heat that can be dissipated depends on the package and its integration into the target board. The “Thermal resistance RΘJA” quantifies these parameters. The power dissipation must be limited so that the average junction temperature does not exceed 125 °C.
The difference between junction temperature and ambient temperature is determined by
∆T = (PINT + PIOSTAT + PIODYN) × RΘJA
The internal power consumption is defined as
PINT = VDDP × IDDP (see Section 4.2.3).
The static external power consumption caused by the output drivers is defined as
PIOSTAT = Σ((VDDP-VOH) × IOH) + Σ(VOL × IOL)
The dynamic external power consumption caused by the output drivers (PIODYN) depends on the capacitive load connected to the respective pins and their switching frequencies.
If the total power dissipation for a given system configuration exceeds the defined limit, countermeasures must be taken to ensure proper system operation:
•Reduce VDDP, if possible in the system
•Reduce the system frequency
•Reduce the number of output pins
•Reduce the load on active output drivers
Data Sheet |
119 |
V2.1, 2008-08 |
w w w . i n f i n e o n . c o m
Published by Infineon Technologies AG