Furber S.ARM system-on-chip architecture.2000

Glossary

memory, and may be used for the main memory in some smaller embedded systems.

TLB Translation Look-aside Buffer, a cache of recently used page table entries which avoids the overhead of page table-walking on every memory access.

UART Universal Asynchronous Receiver/Transmitter; a peripheral device that interfaces a serial line (typically with an RS232 signalling protocol) to a processor bus.

USB Universal Serial Bus; a standard interface on more recent PCs that supports the connection of various peripherals. It uses a high-speed serial protocol and an electrical interface that allows devices to be connected and disconnected while the machine is running (that is, it is 'hot-pluggable').

VHDL VHSIC Hardware Description Language (where VHSIC expands to Very High-Speed Integrated Circuit); a standard language for describing hardware at a behavioural or structural level which is supported by most semiconductor design tool companies.

VLSI Very Large Scale Integration; the process of putting a lot of transistors onto a single chip. There was an

409

attempt to categorize chip transistor counts as SSI, MSI, LSI (Small, Medium and Large Scale Integration), VLSI, and so on, on the basis of orders of magnitude, but process technology advanced faster than new terms could be coined. The next term, ULSI (Ultra Large Scale Integration) never gained widespread use, and would probably now be obsolete anyway.

VLSI Technology, Inc. VLSI Technology, Inc., sometimes abbreviated to just VLSI, manufactured the first ARM chips designed at Acorn Computers and, with Acorn and Apple, established ARM Limited as a separate company in 1990. VLSI was the first ARM semiconductor partner and manufactures a range of ARM-based CPUs and system chips. It is now owned by Philips Semiconductors.

VM Virtual Memory; the address space that the program runs in which is mapped to physical memory by the MMU. The virtual space may be larger than the physical space, and parts of the virtual space may be paged out onto a hard disk or may not exist anywhere.

VRAM Video Random Access Memory; a form of

DRAM with on-chip shift registers to give high-bandwidth access to sequential data for generating video displays.

Index

abort recovery 331-2 abort timing 146 absolute addressing 17 abstraction 3-7, 152 access permissions 305-8 accessing operands 168-9 accessing state 235-6 accumulator (ACC) register 7 Acorn Computers 36, 348 activity factors (of a logic gate) 30 adder design 87-92

carry arbitration 91—2 carry look-ahead 88, 89 carry-save 94 carry-select 88-9, 90 ripple-carry 88

addition/subtraction 51,243^,400-1 address incrementer 214-16 address non-determinism 378 address space model 180-1 address translation 303 addressing

absolute 17 auto-indexing 58 base plus index 17

base plus offset 17,58-9 base plus scaled index 17 block copy 61-3 exceptions 111 immediate 17

indirect 17

initializing pointer 56-7 instruction formats 14—16 modes 17

multiple register data transfers 60 number of addresses 14-16 post-indexed 59

pre-indexed 58

register load and store instructions 57—8 register-indirect 17, 56

stack 17,60-1

AHB (Advanced High-performance Bus) 217, 220 alignment checking 306 ALU design 12-13 AMBA (Advanced Microcontroller Bus Architecture) 216-20,

232 AMULET processor cores

374-97

AMULET1 377-81,397

AMULET2 381^t, 397 AMULET2e 384-6 AMULET3 387-90,396,397 AMULET3H 390,392,393-6

DRACO telecommunications controller 390-6

self-timed design 375—7 analogue to digital converters (ADCs) 350-1 AND gate 399 ANSI C data types 157-8 APB (Advanced Peripheral Bus) 217, 219-20 APCS (ARM Procedure Call Standard) 176-9 applications

ARM7TDMI 255-6 ARMS 258 ARM9TDMI 262-3 ARM10TDMI 266 ARM7500 361-3

embedded applications 347 SA-1100 370

Thumb instruction set 189, 203-4 arbitration 217-18 architectural inheritance 37-8 architectural variants 147—8 argument passing 179 arguments 176 arithmetic operations 51, 243^t, 400-1

see also adder design; multiplication arithmetic-logic unit (ALU) 7, 88-90 ARM 10200 342-3 ARM1020E 341-2 ARM10TDMI 256,263-6,344 ARM2 88, 147 ARM3 147,279-82 ARM6 74,88,90-1,96, 147 ARM60 148 ARM600 148,282-3 ARM610 148 ARM7 74,256 ARM7100 364-8 ARM710T 318-22 ARM720T 318,322 ARM740T 318,322-3 ARM7500 360-3 ARM7500FE 360-3 ARM7TDMI 101-2, 248-56, 353 ARM7TDMI-S 255 ARM8 95,256-9 ARM810 323-6 ARM920T 335-7 ARM940T 337-9 ARM946E-S 339^1 ARM966E-S 339^11 ARM9E-S 241,245,263 ARM9TDMI 79,91,245,256,260-3 ARM assembler 45 ARM Development Board 44, 46 ARM instructions see instructions; Thumb instruction set ARM Limited 35, 36, 348

413

ARM Procedure Call Standard (APCS) 176-9 ARM Project Manager 46

ARM Software Development Toolkit 46-7

ARM system control coprocessor 293-4 ARMsd 44, 45

ARMulator 44, 45-6, 225 arrays 157, 169-70

ASB (Advanced System Bus) 217 ASCII 156

assemblers 45

assembly language programming 49—71 assembly-level abstraction 152 associativity 344—5

asynchronous design styles 375-7 auto-indexing 58

barrel shifter 92-3

base plus index addressing 17

base plus offset addressing 17, 58—9 base plus scaled index addressing 17 base registers 17, 56

BBC microcomputer 36 Berkeley RISC designs 37 big-endian 41, 105-6, 157 binary notation 154,400-1 bit 400-1

bit-wise logical operations 51 bitfields 157

block copy addressing 61-3

Bluetooth 355-60 Boolean algebra 154,400

boundary scan test architecture 226-32 branch instructions 63, 66, 84-5

Branch and Branch with Link 113-15

Branch, Branch with Link and eXchange 115-17 conditional branches 63-4

delayed branches 24, 37-8 Thumb instruction set 191-4 breakpoint instruction 140-1,200-1

buffers control 308

hit-under-miss support 341 jump trace buffer 382-3

write buffers 308, 321-2, 333^, 336, 339, 342 buses 216-20

AHB (Advanced High-performance Bus) 217,220

AMBA (Advanced Microcontroller Bus Architecture) 216-20, 232

APB (Advanced Peripheral Bus) 217, 219-20 arbitration 217-18

ARM7TDMI 253

ARM1020E 342

ASB (Advanced System Bus) 217 MARBLE on-chip bus 392 modes 219

SA-1100 370 signals 208

test interface 219 transfers 218 byte

ordering 157

C compiler 19-20,44 C functions 176 cache 269, 272-83, 308

AMULET2e 384-5 ARM3 279-82 ARM600 282-3 ARM710T 318-20 ARM920T 335-6 ARM940T 337-9 ARM946E-S 339^0 ARM1020E 341 associativity 344—5 controls 308 direct-mapped 273-5 double-bandwidth 324-5 fully associative 277-8 Harvard 272

hit rate 273

input/output interactions 313-14, 314-15 line of data 273

line length 345 memory bandwidth 344 miss rate 273 organization 273 performance metrics 273 power efficiency 320 primary role of 317 set-associative 275-7 speeds 320

StrongARMSA-110 332,333 unified 272, 280

virtual and physical 287-8

write strategies 278, 345 callee-saved registers 178 caller-saved registers 178 CAM (content addressed memory) 277, 281-2 carry arbitration adder 91—2 carry look-ahead adder 88, 89 carry-save adder 94 carry-select adder 88-9, 90 chaining 235 characters 156, 157 chunked stack model 182 CISC (Complex Instruction Set Computers) 20 clocking scheme 86 clocks 26-7,351,402

ARM10TDMI 263-5 ARM7TDMI 249 ARMS 256

clock skew 375 self-timed design 375—7

CMOS technology 4,28-31 codec 350

combinatorial logic 402 comparison operations 52 compilers 19-20,44,333 Complex Instruction Set Computers (CISCs) 20 computer architecture 2 computer logic 399 computer organization 2 condition codes 18, 53-5, 112

Index

condition mnemonics 111—12 conditional branches 18,63-4 conditional execution 65, 111-12 conditional statements 170-2

content addressed memory (CAM) 277, 281-2 context switching 167-8, 310-11

control flow instructions 17-18,63-8 control logic 10-11, 209-11

control structures 99-100 coprocessors

architecture 101

ARM system control coprocessor 293—4 data operations 136-7,137-8

data transfers 138-9 FPA10 168-8, 360-1 handshake 101 instructions 136-7 interfaces 101-3, 254, 261 Piccolo coprocessor 240 register transfers 139-40

VFP10 168, 342-3 copy-back 278 cores see processor cores count leading zeros (CLZ) 124-5 counter-timers 222

CP15 MMU registers 294-7,298-302 CPSR (Current Program Status Register) 40 CPU cores see processor cores cross-development toolkit 43—4

D-type latches 402-3 data aborts 144-7 data alignment 183 data cache 332

data forwarding 80-1 data operations 136-7

data processing instructions 50-5, 82,119-22, 195-7 data registers 227

datastorage 183

data transfer instructions 55-63, 82^t, 102, 125-30, 136 coprocessor data transfers 138—9

Thumb instruction set 198-200 datatypes 105, 153-63

FPA10 data types 163-8,360-1 VFP10 168,342-3

datapath design 9-10 datapath layout 98-9 datapath operation 10 datapath timing 86-7 debug comms 236 debugging 232-6,233, 253^t

embedded trace macrocell 237-9 VWS22100 GSM chip 355

decimal numbers 153 decode logic 388-9 decoders 99-100 delayed branches 24, 37-8 demand-paged virtual memory 287 denormalized numbers 160 design for test see testing design trade-offs 19-24

415

desktop debugging 232-3 destination of results 14 development tools 43—7 device drivers 315 digital radio 359-60

Digital Signal Processing (DSP) 18, 239-40, 352-3 Direct Memory Access (DMA) 312-13 direct-mapped cache 273-5

DMA (Direct Memory Access) 312-13 domains 302-3

double precision numbers 161 double-bandwidth cache 324-5 double-bandwidth memory 257 do..while loops 174

DRACO telecommunications controller 390-6

DRAM (dynamic random access memory) 213-14, 215, 272 DSP (Digital Signal Processing) 18, 239-40, 352-3 dynamic instruction frequency 21

early aborts 146 edge-triggered latches 403 electromagnetic interference 375, 391 electronics technology 2 embedded applications 347 embedded debugging 233 embedded systems 144, 293 embedded trace macrocell 237-9 Embedded-ICE 230,234-6 emulator (ARMulator) 44, 45-6, 225 endianness 41, 106-7, 157 enumerated data types 157 Ericsson 355—60 exceptions 107-11, 191 execution 82-5 exponent bias 160 expressions 168-70 extended packed decimal numbers 162 extensions 13 external memory interface 392—3 EXTEST (JTAG instruction) 229,231

fan-in (of logic gates) 399 Fast Interrupt Request (FIQ) 313 finite state machine (FSM) 9 FIQ (Fast Interrupt Request) 313 floating-point

ARM architecture 163-8 datatypes 158-63,342-3 registers 165-6,311 units 360-1

FPA 10 coprocessor 163-8,360-1 VFP10 coprocessor 168, 342-3 for loops 173 forwarding paths 331 FPA 10 data types 163-8,360-1 fully associative

cache 277-8 functions 157, 175-80

gate abstraction 5-6 gate-level design 6-7 gated clocks 30

416

half-word data transfer instructions 127-9

'Halt'instruction 383-4 hard macrocells 100-1 hardware prototyping 223-4

Harvard cache 272 hazard, read-after-write 22 heap 180

Hello World program 69-71 hexadecimal notation 154 hierarchy of components 175 high-level languages 151-85 hit-under-miss support 341

I/O (input/output) 42-3,312-15,361 IDCODE (JTAG instruction) 229 idempotency 103,312 IEEE 754 Standard 159 if...else 170-1 immediate addressing 17 immediate operands 52 implementation 86-101,201-3

adder design 87-92 barrel shifter 92-3 clocking scheme 86 control structures 99-100

coprocessor interface 101-3 datapath layout 98-9 datapath timing 86-7 multiplier design 93-6 register bank 96-8

In-Circuit Emulator (ICE) 207, 230, 233-6 index register 17 indirect addressing 17 initialization 10,252 initializing address pointer 56-7 input/output (I/O) 42-3, 312-15, 361 instruction cache 332 instruction decoders 99 instruction mapping 201-3 instruction register (IR) 7, 227-8 instructions 42, 105^19

breakpoint 140-1 condition codes 112

conditional execution 65, 111-13 control flow 63-8

coprocessor 135—40 count leading zeros 123-4 data operations 136-7

data processing 50-5, 82, 119-22

data transfer 55-63, 82^t, 102, 125-30, 136, 138-9 design 14-19

exceptions 108-12 execution 82-5 frequencies 166 'Halt' 383-4

load instructions 57—8 MU0 processors 8

register transfer 130-35, 139^1, 165-6 software interrupt 117-19

store instructions 57—8 SWAP instruction 309

Index

swap memory and register instructions (SWP) 132-3 types of 16

unused instruction space 142-3 usage measurements 21

see also branch instructions; Thumb instruction set integer unit organization 258, 259 integers 155 interrupt controller 222 interrupt latency 313 INTEST (JTAG instruction) 229 IRQ 107-10 ISDN Subscriber Processor 349-52

JTAG boundary scan test architecture 226-32,254 jump tables 67-8 jump trace buffer 382-3 JumpStart tools 47

keyboard interfaces 351

latches 402-3 late aborts 161 latency 313,314

LDM data abort 145 leaf routines 175—6 level signalling 377 libraries 185

line length 345 link register 66 linker 45

little-endian 41, 106-7, 157 load instructions 57-8 load-store architecture 41, 165 logic

combinatorial 402 computer logic 399 control logic 10-11,209-11 design 8-9

PLA (programmable logic array) 99 symbols 5

logic gates 4-5, 399-400 logical operations 51 loops 173^t low power see power management

macrocells 100-1

testing 230-2 MARBLE on-chip bus 392 memory 180-4

address space model 180-1 bandwidth 344

double-bandwidth 257 bottlenecks 79

content addressed memory (CAM) 277, 281-2 controllers 340,361,369

cost 270

Direct Memory Access (DMA) 312-13

DRAM (dynamic random access memory) 213-14, 215, 272 efficiency 183-4

external memory interface 392-3 faults 143-7

granularity 302 hierarchy 269-88

interfaces 208-16,251-2,350 mapping 222,292,312 on-chip memory 271

organization 40-1, 105-6, 393^t read-sensitive locations 312 size and speed 270,272

timing accesses 215, 385-6

see also cache memory management unit (MMU) 283-8,291, 294, 317, 345

ARM710T 321

ARM1020E 342

ARM920T 336-7

ARM940T 337

ARM MMU architecture 302-8 CP15 MMU registers 294-7, 298-302 paging 285-6

restartable instructions 287 segmentation 284-5 StrongARMSA-110 334

translation look-aside buffers (TLB) 287 virtual memory 286-7

virtual and physical caches 287—8

MIPS (Microprocessor without Interlocking Pipeline Stages) 37 MMU see memory management unit (MMU) mnemonics 111-12 modes 17

multi-user systems 291

multiple register transfer instructions 60, 129-31 multiplexers 401 multiplication 55, 93-6, 122-4, 242-3

StrongARMSA-110 332 MU0 processors 7-13

ALU design 12-13 components 7-8 control logic 10-11 datapath design 9-10 datapath operation 10 extensions 13 initialization 10 instruction set 8 logic design 8-9

register transfer level design 10 mutual exclusion 309

N-Trace 239 NaN (Not a Number) 160 NAND 4-5, 399^(00 never condition (NV) 111 non re-entrant code 178-9 normalized numbers 159,160 number of addresses 14-16 numbers 153, 155-6

binary numbers 400—1 floating-point 158-63 ranges 154-5

Oak DSP core 352-3 on-chip debug 261 on-chip memory 271

OneCVWS22100 GSM chip 352-5

Open Microprocessor systems Initiative (OMI) 397 operands 50-3, 168-9

operating system support 290—315 ARM MMU architecture 302-8

ARM system control coprocessor 293-4 context switching 310—11

CP15 registers 294-7,298-302 device drivers 315

embedded systems 293 input/output 312-15 memory management 291 multi-user systems 291 protection 291-2,294-8 resource allocation 292,315 single-user systems 292-3 synchronization 308-9

orthogonal instructions 16

packed decimal numbers 161-2 packed structures 157,184 padding 183

page absent 143 page protected 143

page translation 304-5 paging 285-6 parameters 176

pause controller 222 PCB testing 229 peripherals 216,370

memory-mapped 312

reference peripheral specification 220-2 physical caches 287-8 physical design 100-1 Piccolo coprocessor 240 piconets 356 pipelining 21-4,26

ARM10TDMI 264

ARM7TDMI 260-1 ARMS 257 ARM9TDMI 260-1 stage organization 78-82 FPA10 pipeline 167 self-timed 377

StrongARMSA-110 329-31

3 stage organization 75—8 PLA (programmable logic array) 99 pointer arithmetic 169 pointer initialization 56-7 pointers 157 post-indexed addressing 59 power management 28-32, 320, 375

ARM7100 365-6

ARM7TDMI 254

ARM9TDMI 262

Bluetooth 357-8 optimization 320-1 VWS22100 GSM chip 355

pre-indexed addressing mode 58 prefetch aborts 144 prefetch units 387-8

418

printable characters 156 printed circuit board (PCB) testing 229 priority information 291 privileged operating modes 106—7 Procedure Call Standard (APCS) 176-9 procedures 175—80 process synchronization 309 processor cores 74, 247

AMULET cores 374-97 ARM7TDMI 255 ARM9TDMI 262

CPU cores 317^*5 debugging 233 DSP cores 239^tO

StrongARMSA-110 328-9 synthesizable 255,263,341

processors

abstraction in hardware design 3-7 components 7—8

definition 2

design trade-offs 19-24 instruction set design 14-19 MU0 processors 7—13 stored-program computers 2, 3 usage measurements 21 program

counter (PC) register 7 program design 71 program hierarchy 175 programmer's model 39-43, 190-1 Project Manager 46 protection 291-2, 294-8 prototyping tools 223-4 pseudo-code 71 Psion Series 5 366-7 public instructions 227-9

Qflag 241-2

r15 119-20

R-S (Reset-Set) flip-flop 402 Rapid Silicon Prototyping 223-4 re-entrant code 178-9 read-after-write pipeline hazard 22

read-sensitive memory locations 312 real numbers 156

real-time debug 237-8

reference peripheral specification 220-2 register bank 75,96-8

register-indirect addressing 17, 56 registers 402,403-4

base registers 17,56 coherency 379

CP15 294-7,298-302 EmbeddedlCE mapping 235 forwarding 381—2

load and store instructions 57—8 locking 379-80

movement operations 51 operands 50-2, 53 protection unit 294-8

transfer instructions 130-37, 139-41, 165-6

Index

transfer level design 10 use convention 177

windows 37 reorder buffer 387 reset controller 222 Reset-Set (R-S) flip-flop 402 resource allocation 292, 315 restartable instructions 287 result returns 179 ripple-carry adder 88 RISC (Reduced Instruction Set Computer) 1, 20, 24-8, 35-6

Berkeley RISC designs 37 ROM (Read Only Memory) 20 Roman numerals 153 RTL design 9

Ruby II Advanced Communication Processor 348—9 run-time environment 185

SA-110 see StrongARM SA-110 SA-1100 368-71

scatternets 356 scheduling 291

section translation 303—4 segmentation 284—5 self-timed design 375—7 self-timed digital systems 374 self-timed signalling 376 semantic gap 19

semaphore 131 sequential circuits 402

sequential memory access 212-13,320 set-associative cache 275-7

shifted register operands 53 short integers 157

signal processing support 239-45 signalling 376-7

signed byte data transfer instructions 128-30 signed integers 155

single precision numbers 159

single word data transfer instructions 125—8 single-cycle execution 38

single-user systems 292—3 SO-interface 350

soft macrocells 100-1 soft memory errors 143—4

software development tools 43-7 software interrupt 117-19,194-5 software tools 239

sound systems 361

SPSRs (Saved Program Status Register) 106, 107 stack

addressing 17, 60—1 behaviour 182—3 chunked stack model 182 and memory use 180

stack-limit checking 178 Standard Test Access Port 226 Stanford MIPS 37 static instruction frequency 21 .status register 132-3