Furber S.ARM system-on-chip architecture.2000

Cache speed

Cache power

Sequential accesses

Power optimization

High-associativity caches give the best hit rate, but require sequential CAM then RAM accesses which limits how fast the cycle time can become. Caches with a lower associativity can perform parallel tag and data accesses to give faster cycle times, and although a direct mapped cache has a significantly lower hit rate than a fully associative one, most of the associativity benefits accrue going from direct-mapped to 2- or 4-way associative; beyond 4-way the benefits of increased associativity are small. However, a fully associative CAM-RAM cache is much simpler than a 4-way associative RAM-RAM cache.

CAM is somewhat power-hungry, requiring a parallel comparison with every entry on each cycle. Segmenting the cache by reducing the associativity a little and activating only a subsection of the CAM reduces the power cost significantly for a small increase in complexity.

In a static RAM the main users of power are the analogue sense-amplifiers. A 4-way cache must activate four times as many sense-amplifiers in the tag store as a direct-mapped cache; if it exploits the speed advantage offered by parallel tag and data accesses, it will also uses four times as many sense-amplifiers in the data store. (RAM-RAM caches can, alternatively, perform serial tag and data accesses to save power, only activating a particular data RAM when a hit is detected in the corresponding tag store.) Waste power can be minimized by using self-timed power-down circuits to turn off the sense-amplifiers as soon as the data is valid, but the power used in the sense-amplifiers is still significant.

Where the processor is accessing memory locations which fall within the same cache line it should be possible to bypass the tag look-up for all but the first access. The ARM generates a signal which indicates when the next memory access will be sequential to the current one, and this can be used, with the current address, to deduce that the access will fall in the same line. (This does not catch every access within the same line, but it catches nearly all of them and is very simple to implement.)

Where an access will be in the same line, bypassing the tag look-up increases the access speed and saves power. Potentially, sequential accesses could use slower sense-amplifiers (possibly using standard logic rather than analogue circuits) and save considerable power, though care must be taken to ensure that an increased voltage swing on the bit lines does not cost more energy than is saved in the sense-amplifiers.

The cache designer must remember that the goal is to minimize the overall system power, not just the cache power. Off-chip accesses cost a lot more energy than on-chip accesses, so the first priority must be to find a cache organization which gives a good hit rate. Deciding between a highly associative CAM—RAM organization or a set-associative RAM—RAM organization requires a detailed investigation of all of the design issues, and may be strongly influenced by low-level circuit issues such as novel ways to build power-efficient sense-amplifiers or CAM hit detectors.

ARM710TMMU

ARM710T write buffer

Exploiting sequential accesses to save power and to increase performance is always a good idea. Typical dynamic execution statistics from the ARM show that 75% of all accesses are sequential, and since sequential accesses are fundamentally easier to deal with, this seems to be a statistic that should not be overlooked. Where power-efficiency is paramount, it may be worth sacrificing performance by making nonsequential accesses take two clock cycles; this will only reduce performance by about 25% and may reduce the cache power requirements by a factor of two or three.

An interesting question for research into low power is to ask whether the best cache organization for power-efficiency is necessarily the same as the best organization for high performance

The ARM710T memory management unit implements the ARM memory management architecture described in Section 11.6 on page 302 using the system control coprocessor described in Section 11.5 on page 298.

The translation look-aside buffer (TLB) is a 64-entry associative cache of recently used translations which accelerates the translation process by removing the need for the 2-stage table look-up in a high proportion of accesses.

The write buffer holds four addresses and eight data words. The memory management unit defines which addresses are bufferable. Each address may be associated with any number of the data words, so the write buffer may hold one word (or byte) of data to write to one address and seven words to write to another address, or two blocks of four words to write to different addresses, and so on. The data words associated with a particular address are written to sequential memory locations starting at that address.

(Clearly multiple data words associated with one address are generated principally by store multiple register instructions, the only other potential source being a data transfer from an external coprocessor.)

The mapping is illustrated in Figure 12.3 on page 322, which shows the first address mapping six data words and the second and third addresses mapping one data word each. The fourth address is currently unused. The write buffer becomes full either when all four addresses are used or when all eight data words are full.

The processor can write into the buffer at the fast (cache) clock speed and continue executing instructions from the cache while the write buffer stores the data to memory at the memory clock rate. The processor is therefore fully decoupled from the memory speed so long as the instructions and data it needs are in the cache and the write buffer is not full when it comes to perform a write operation. The write buffer gives a performance benefit of around 15% for a modest hardware cost.

The principal drawback of the write buffer is that it is not possible to recover from external memory faults caused by buffered writes since the processor state is not recoverable. The processor can still support virtual memory since translation faults are detected in the on-chip MMU, so the exception is raised before the data gets to the

ARM720T

ARM740T

The ARM720T is very similar to the ARM710T with the following extensions:

•Virtual addresses in the bottom 32 Mbytes of the address space can be relocated to the 32 Mbyte memory area specified in the ProcessID register (CP15 register 13).

•The exception vectors can be moved from the bottom of memory to OxffffOOOO, thereby preventing them from being translated by the above mechanism. This function is controlled by the 'V bit in CP15 register 1.

These extensions are intended to enhance the ability of the CPU core to support the Windows CE operating system. They are implemented in the CP15 MMU control registers described in Section 11.5 on page 298.

The ARM740T differs from the ARM710T only in having a simpler memory protection unit in place of the 710T's memory management unit. The memory protection unit implements the architecture described in Section 11.4 on page 297 using the system control coprocessor described in Section 11.3 on page 294.

The protection unit does not support virtual to physical memory address translation, but provides basic protection and cache control functionality in a lower cost form. This