Furber S.ARM system-on-chip architecture.2000

If the data and coefficients are always in on-chip memory, the loop takes 19 clock

cycles if executed from on-chip RAM, with 14 additional wait state cycles if executed

from two wait state off-chip RAM.

The use of on-chip RAM therefore speeds the loop up by around 75%.

Note that this speed-up is a lot less than the factor three that might be expected

from simply comparing memory access speeds.

Exercise 13.1.1

Estimate the power saving that results from using the on-chip RAM. (Assume that

on-chip accesses cost 2 nJ and off-chip accesses 10 nJ.)

Exercise 13.1.2

Repeat the estimates assuming the external memory is restricted to!6 bits wide.

Exercise 13.1.3

Repeat the estimates for both 32and 16-bit external memory assuming that the

processor supports Thumb mode (and the program is rewritten to use Thumb

instructions) and high-speed multiplication.

Example 13.2

Survey the designs presented in this chapter and summarize the

power-saving techniques employed on the system chips

described here.

Firstly, all the system chips display a high level of integration which saves power

whenever two modules on the same chip exchange data.

All the chips are based around an ARM core which is, itself, very power-efficient.

Though none of the chips has enough on-chip memory to remove the need for

off-chip memory completely, several have a few kilobytes of on-chip RAM which can

be loaded with critical routines to save power (and improve performance).

Several of the chips incorporate clock control circuitry which reduces the clock fre-

quency (or stops the clock altogether) when the chip is not fully loaded, and switches

the clock to individual modules off when they are inactive.

The chips are mainly based upon static or pseudo-static CMOS technology where,

with a little care, digital circuits only consume power when they switch. Some of the

chips also incorporate analogue functions which require continuous bias currents, so

these circuits can usually be powered down when they are inactive.

Exercise 13.2.1

In embedded systems there is usually no 'reset' button to restart a system that has

crashed. What techniques are used to recover from software crashes?

Exercise 13.2.2

Several of the chips described in this chapter incorporate counter/timer modules.

What are these used for?

Exercise 13.2.3

The ARM7500 has an on-chip cache, AMULET2e (see Section 14.4 on page 384)

has on-chip memory which can be configured either as a cache or as directly

addressed memory, and Ruby II and VIP simply have directly addressed on-chip

memory. Explain the difference between on-chip RAM and an on-chip cache and

explain why the designers of these chips made the choices that they did.

Self-timed

signalling

Transition

signalling

Figure 14.2 Level-signalling communication protocol.

Transition signalling was used on AMULET 1 since it is conceptually cleaner;

every transition has a role and its timing is therefore determined by the circuit's

function. It also uses the minimum number of transitions, and should therefore be

power-efficient. However, the CMOS circuits used to implement transition control are

relatively slow and inefficient, so AMULET2 and AMULETS use level signalling

which employs circuits which are faster and more power-efficient despite using twice

the number of transitions, but leave somewhat arbitrary decisions to be taken about the

timing of the recovery (return-to-zero) phases in the protocol.

Self-timed

An asynchronous pipelined processing unit can be constructed using self-timing tech-

pipelines

niques to allow for the processing delay in each stage and one of the above protocols

to send the result to the next stage. When the circuit is correctly designed variable

processing and external delays can be accommodated; all that matters is the local

sequencing of events (though long delays will, of course, lead to low performance).

Unlike a clocked pipeline, where the whole pipeline must always be clocked at a

rate determined by the slowest stage under worst-case environmental (voltage and

temperature) conditions and assuming worst-case data, an asynchronous pipeline will

operate at a variable rate determined by current conditions. It is possible to allow rare

worst-case conditions to cause a processing unit to take a little longer. There will be

some performance loss when these conditions do arise, but so long as they are rare

enough the impact on overall performance will be small.

Figure 14.3 AMULET1 internal organization.

pipelines, all operating in their own time at their own speed. These pipelines might

appear to introduce unacceptably long latencies into the processor but, unlike a syn-

chronous pipeline, an asynchronous pipeline can have a very low latency.

The operation of the processor begins with the address interface issuing instruction

fetch requests to the memory. The address interface has an autonomous address

incre-menter which enables it to prefetch instructions as far ahead as the capacities of

the various pipeline buffers allow.

Address

Instructions that need to generate a new memory address, such as data transfer instruc-

non-determin

tions and unpredicted branches, calculate the new address in the execution pipeline and

ism

then send it to the address interface. Since it arrives with arbitrary timing relative to the

internal incrementing loop within the address interface, the point of insertion of the

new address into the address stream is non-deterministic, so the processor's depth of

prefetch beyond a branch instruction is fundamentally non-deterministic.