
- •CONTENTS
- •PREFACE
- •LIST OF FIGURES
- •INTRODUCTION
- •1.1 WHAT IS TIME?
- •1.2 SIMULATION
- •1.3 TESTING
- •1.4 VERIFICATION
- •1.6 USEFUL RESOURCES
- •2.1 SYMBOLIC LOGIC
- •2.1.1 Propositional Logic
- •2.1.2 Predicate Logic
- •2.2 AUTOMATA AND LANGUAGES
- •2.2.1 Languages and Their Representations
- •2.2.2 Finite Automata
- •2.3 HISTORICAL PERSPECTIVE AND RELATED WORK
- •2.4 SUMMARY
- •EXERCISES
- •3.1 DETERMINING COMPUTATION TIME
- •3.2 UNIPROCESSOR SCHEDULING
- •3.2.1 Scheduling Preemptable and Independent Tasks
- •3.2.2 Scheduling Nonpreemptable Tasks
- •3.2.3 Nonpreemptable Tasks with Precedence Constraints
- •3.2.5 Periodic Tasks with Critical Sections: Kernelized Monitor Model
- •3.3 MULTIPROCESSOR SCHEDULING
- •3.3.1 Schedule Representations
- •3.3.3 Scheduling Periodic Tasks
- •3.4 AVAILABLE SCHEDULING TOOLS
- •3.4.2 PerfoRMAx
- •3.4.3 TimeWiz
- •3.6 HISTORICAL PERSPECTIVE AND RELATED WORK
- •3.7 SUMMARY
- •EXERCISES
- •4.1 SYSTEM SPECIFICATION
- •4.2.1 Analysis Complexity
- •4.3 EXTENSIONS TO CTL
- •4.4 APPLICATIONS
- •4.4.1 Analysis Example
- •4.5 COMPLETE CTL MODEL CHECKER IN C
- •4.6 SYMBOLIC MODEL CHECKING
- •4.6.1 Binary Decision Diagrams
- •4.6.2 Symbolic Model Checker
- •4.7.1 Minimum and Maximum Delays
- •4.7.2 Minimum and Maximum Number of Condition Occurrences
- •4.8 AVAILABLE TOOLS
- •4.9 HISTORICAL PERSPECTIVE AND RELATED WORK
- •4.10 SUMMARY
- •EXERCISES
- •VISUAL FORMALISM, STATECHARTS, AND STATEMATE
- •5.1 STATECHARTS
- •5.1.1 Basic Statecharts Features
- •5.1.2 Semantics
- •5.4 STATEMATE
- •5.4.1 Forms Language
- •5.4.2 Information Retrieval and Documentation
- •5.4.3 Code Executions and Analysis
- •5.5 AVAILABLE TOOLS
- •5.6 HISTORICAL PERSPECTIVE AND RELATED WORK
- •5.7 SUMMARY
- •EXERCISES
- •6.1 SPECIFICATION AND SAFETY ASSERTIONS
- •6.4 RESTRICTED RTL FORMULAS
- •6.4.1 Graph Construction
- •6.5 CHECKING FOR UNSATISFIABILITY
- •6.6 EFFICIENT UNSATISFIABILITY CHECK
- •6.6.1 Analysis Complexity and Optimization
- •6.7.2 Timing Properties
- •6.7.3 Timing and Safety Analysis Using RTL
- •6.7.5 RTL Representation Converted to Presburger Arithmetic
- •6.7.6 Constraint Graph Analysis
- •6.8 MODECHART SPECIFICATION LANGUAGE
- •6.8.1 Modes
- •6.8.2 Transitions
- •6.9.1 System Computations
- •6.9.2 Computation Graph
- •6.9.3 Timing Properties
- •6.9.4 Minimum and Maximum Distance Between Endpoints
- •6.9.5 Exclusion and Inclusion of Endpoint and Interval
- •6.10 AVAILABLE TOOLS
- •6.11 HISTORICAL PERSPECTIVE AND RELATED WORK
- •6.12 SUMMARY
- •EXERCISES
- •7.1.1 Timed Executions
- •7.1.2 Timed Traces
- •7.1.3 Composition of Timed Automata
- •7.1.4 MMT Automata
- •7.1.6 Proving Time Bounds with Simulations
- •7.2.1 Untimed Traces
- •7.2.2 Timed Traces
- •7.3.1 Clock Regions
- •7.3.2 Region Automaton
- •7.4 AVAILABLE TOOLS
- •7.5 HISTORICAL PERSPECTIVE AND RELATED WORK
- •7.6 SUMMARY
- •EXERCISES
- •TIMED PETRI NETS
- •8.1 UNTIMED PETRI NETS
- •8.2 PETRI NETS WITH TIME EXTENSIONS
- •8.2.1 Timed Petri Nets
- •8.2.2 Time Petri Nets
- •8.3 TIME ER NETS
- •8.3.1 Strong and Weak Time Models
- •8.5.1 Determining Fireability of Transitions from Classes
- •8.5.2 Deriving Reachable Classes
- •8.6 MILANO GROUP’S APPROACH TO HLTPN ANALYSIS
- •8.6.1 Facilitating Analysis with TRIO
- •8.7 PRACTICALITY: AVAILABLE TOOLS
- •8.8 HISTORICAL PERSPECTIVE AND RELATED WORK
- •8.9 SUMMARY
- •EXERCISES
- •PROCESS ALGEBRA
- •9.1 UNTIMED PROCESS ALGEBRAS
- •9.2 MILNER’S CALCULUS OF COMMUNICATING SYSTEMS
- •9.2.1 Direct Equivalence of Behavior Programs
- •9.2.2 Congruence of Behavior Programs
- •9.2.3 Equivalence Relations: Bisimulation
- •9.3 TIMED PROCESS ALGEBRAS
- •9.4 ALGEBRA OF COMMUNICATING SHARED RESOURCES
- •9.4.1 Syntax of ACSR
- •9.4.2 Semantics of ACSR: Operational Rules
- •9.4.3 Example Airport Radar System
- •9.5 ANALYSIS AND VERIFICATION
- •9.5.1 Analysis Example
- •9.5.2 Using VERSA
- •9.5.3 Practicality
- •9.6 RELATIONSHIPS TO OTHER APPROACHES
- •9.7 AVAILABLE TOOLS
- •9.8 HISTORICAL PERSPECTIVE AND RELATED WORK
- •9.9 SUMMARY
- •EXERCISES
- •10.3.1 The Declaration Section
- •10.3.2 The CONST Declaration
- •10.3.3 The VAR Declaration
- •10.3.4 The INPUTVAR Declaration
- •10.3.5 The Initialization Section INIT and INPUT
- •10.3.6 The RULES Section
- •10.3.7 The Output Section
- •10.5.1 Analysis Example
- •10.6 THE ANALYSIS PROBLEM
- •10.6.1 Finite Domains
- •10.6.2 Special Form: Compatible Assignment to Constants,
- •10.6.3 The General Analysis Strategy
- •10.8 THE SYNTHESIS PROBLEM
- •10.8.1 Time Complexity of Scheduling Equational
- •10.8.2 The Method of Lagrange Multipliers for Solving the
- •10.9 SPECIFYING TERMINATION CONDITIONS IN ESTELLA
- •10.9.1 Overview of the Analysis Methodology
- •10.9.2 Facility for Specifying Behavioral Constraint Assertions
- •10.10 TWO INDUSTRIAL EXAMPLES
- •10.10.2 Specifying Assertions for Analyzing the FCE Expert System
- •Meta Rules of the Fuel Cell Expert System
- •10.11.1 General Analysis Algorithm
- •10.11.2 Selecting Independent Rule Sets
- •10.11.3 Checking Compatibility Conditions
- •10.12 QUANTITATIVE TIMING ANALYSIS ALGORITHMS
- •10.12.1 Overview
- •10.12.2 The Equational Logic Language
- •10.12.3 Mutual Exclusiveness and Compatibility
- •10.12.5 Program Execution and Response Time
- •10.12.8 Special Form A and Algorithm A
- •10.12.9 Special Form A
- •10.12.10 Special Form D and Algorithm D
- •10.12.11 The General Analysis Algorithm
- •10.12.12 Proofs
- •10.13 HISTORICAL PERSPECTIVE AND RELATED WORK
- •10.14 SUMMARY
- •EXERCISES
- •11.1 THE OPS5 LANGUAGE
- •11.1.1 Overview
- •11.1.2 The Rete Network
- •11.2.1 Static Analysis of Control Paths in OPS5
- •11.2.2 Termination Analysis
- •11.2.3 Timing Analysis
- •11.2.4 Static Analysis
- •11.2.5 WM Generation
- •11.2.6 Implementation and Experiment
- •11.3.1 Introduction
- •11.3.3 Response Time of OPS5 Systems
- •11.3.4 List of Symbols
- •11.3.5 Experimental Results
- •11.3.6 Removing Cycles with the Help of the Programmer
- •11.4 HISTORICAL PERSPECTIVE AND RELATED WORK
- •11.5 SUMMARY
- •EXERCISES
- •12.1 INTRODUCTION
- •12.2 BACKGROUND
- •12.3 BASIC DEFINITIONS
- •12.3.1 EQL Program
- •12.3.4 Derivation of Fixed Points
- •12.4 OPTIMIZATION ALGORITHM
- •12.5 EXPERIMENTAL EVALUATION
- •12.6 COMMENTS ON OPTIMIZATION METHODS
- •12.6.1 Qualitative Comparison of Optimization Methods
- •12.7 HISTORICAL PERSPECTIVE AND RELATED WORK
- •12.8 SUMMARY
- •EXERCISES
- •BIBLIOGRAPHY
- •INDEX

168 REAL-TIME LOGIC, GRAPH-THEORETIC ANALYSIS, AND MODECHART
i@(↑ ICP I50NFC SENSOR, i + 1) − 20 ≤ @(↑ ICP I50NFC SENSOR, i)
i@(↑ FCP I50NFC, i + 1) − 20 ≤ @(↑ FCP I50NFC, i)
i@(↑ FCP P50NFC, i + 1) − 20 ≤ @(↑ FCP P50NFC, i)
Safety assertion:
i@((↓ ICP I50FC CMDS, i) ≤ @(↑ ICP I50FC SENSOR, i) + 10
(↓ ICP I10FC CMDS, i) ≤ @(↑ ICP I10FC SENSOR, i) + 50)
;50 Hz and 10 Hz loops must maintain a maximum 10 ms and 50 ms
;“transport lag,” respectively, between sensor input and
;effector output
Negation of safety assertion in RTL:
i@((↑ ICP I50FC SENSOR, i) + 10 < @(↓ ICP I50FC CMDS, i) (↑ ICP I10FC SENSOR, i) + 50 < @(↓ ICP I10FC CMDS, i))
6.7.5 RTL Representation Converted to Presburger Arithmetic
We now convert the RTL formulas into the Presburger arithmetic format to aid in subsequent graphing. The notation convention is to use an “S ” or an “E ” to represent the start or end task events, respectively.
Presburger Arithmetic Representation:
Workloads:
; 50 Hz FC workloads
E ICP I50FC SENSOR(i) − 2 ≤ S ICP I50FC SENSOR(i)
E FCP I50FC(i) − 1 ≤ S FCP I50FC(i)
E FCP P50FC(i) − 5 ≤ S FCP P50FC(i)
E FCP O50FC(i) − 1 ≤ S FCP O50FC(i)
E ICP I50FC CMDS(i) − 1 ≤ S ICP I50FC CMDS(i)
; 10 Hz FC workloads
E ICP I10FC SENSOR(i) − 2 ≤ S ICP I10FC SENSOR(i)
E FCP I10FC(i) − 1 ≤ S FCP I10FC(i)
E FCP P10FC(i) − 40 ≤ S FCP P10FC(i)
E FCP O10FC(i) − 1 ≤ S FCP O10FC(i)
E ICP I10FC CMDS(i) − 1 ≤ S ICP I10FC CMDS(i)
; 50 Hz NFC workloads
E ICP I50NFC SENSOR(i) − 5 ≤ S ICP I50NFC SENSOR(i)

INDUSTRIAL EXAMPLE: NASA X-38 CREW RETURN VEHICLE |
169 |
E FCP I50NFC(i) − 1 ≤ S FCP I50NFC(i)
E FCP P50NFC(i) − 2 ≤ S FCP P50NFC(i)
precedence:
;precedence between start and stop events
;50 Hz FC workloads
S ICP I50FC SENSOR(i) ≤ E ICP I50FC SENSOR(i)
S FCP I50FC(i) ≤ E FCP I50FC(i)
S FCP P50FC(i) ≤ E FCP P50FC(i)
S FCP O50FC(i) ≤ E FCP O50FC(i)
SICP I50FC CMDS(i) ≤ E ICP I50FC CMDS(i)
;10 Hz FC workloads
SICP I10FC SENSOR(i) ≤ E ICP I10FC SENSOR(i)
S FCP I10FC(i) ≤ E FCP I10FC(i)
S FCP P10FC(i) ≤ E FCP P10FC(i)
S FCP O10FC(i) ≤ E FCP O10FC(i)
SICP I10FC CMDS(i) ≤ E ICP I10FC CMDS(i)
;50 Hz NFC workloads
SICP I50NFC SENSOR(i) ≤ E ICP I50NFC SENSOR(i)
S FCP I50NFC(i) ≤ E FCP I50NFC(i)
SFCP P50NFC(i) ≤ E FCP P50NFC(i)
;precedence between end of first task and beginning of next task
;50 Hz FC precedence relations
EICP I50FC SENSOR(i) ≤ S FCP I50FC(i)
E FCP I50FC(i) ≤ S FCP P50FC(i)
E FCP P50FC(i) ≤ S FCP O50FC(i)
EFCP O50FC(i) ≤ S ICP I50FC CMDS(i)
;10 Hz FC precedence relations
EICP I10FC SENSOR(i) ≤ S FCP I10FC(i)
E FCP I10FC(i) ≤ S FCP P10FC(i)
E FCP P10FC(i) ≤ S FCP O10FC(i)
E FCP O10FC(i) ≤ S ICP I10FC CMDS(i)

170 REAL-TIME LOGIC, GRAPH-THEORETIC ANALYSIS, AND MODECHART
; 50 Hz NFC precedence relations
E ICP I50NFC SENSOR(i) ≤ S FCP I50NFC(i)
EFCP I50NFC(i) ≤ S FCP P50NFC(i)
;precedence between beginning of prior task and beginning of next task
SFCP I50FC(i) − 2 ≤ S ICP I50FC SENSOR(i)
S FCP P50FC(i) − 1 ≤ S FCP I50FC(i)
S FCP O50FC(i) − 5 ≤ S FCP P50FC(i)
S ICP I50FC CMDS(i) − 1 ≤ S FCP O50FC(i)
S FCP I10FC(i) − 2 ≤ S ICP I10FC SENSOR(i)
S FCP P10FC(i) − 1 ≤ S FCP I10FC(i)
S FCP O10FC(i) − 40 ≤ S FCP P10FC(i)
S ICP I10FC CMDS(i) − 1 ≤ S FCP O10FC(i)
S FCP I50NFC(i) − 5 ≤ S ICP I50NFC SENSOR(i)
S FCP P50NFC(i) − 1 ≤ S FCP I50NFC(i)
periodicity:
; 50 Hz FC tasks, p = 20
S ICP I50FC SENSOR(i) + 20 ≤ S ICP I50FC SENSOR(i + 1)
S FCP I50FC(i) + 20 ≤ S FCP I50FC(i + 1)
S FCP P50FC(i) + 20 ≤ S FCP P50FC(i + 1)
S FCP O50FC(i) + 20 ≤ S FCP O50FC(i + 1)
S ICP I50FC CMDS(i) + 20 ≤ S ICP I50FC CMDS(i + 1)
S ICP I50FC SENSOR(i + 1) − 20 ≤ S ICP I50FC SENSOR(i)
S FCP I50FC(i + 1) − 20 ≤ S FCP I50FC(i)
S FCP P50FC(i + 1) − 20 ≤ S FCP P50FC(i)
S FCP O50FC(i + 1) − 20 ≤ S FCP O50FC(i)
S ICP I50FC CMDS(i + 1) − 20 ≤ S ICP I50FC CMDS(i)
; 10 Hz FC tasks, p = 100
S ICP I10FC SENSOR(i) + 100 ≤ S ICP I10FC SENSOR(i + 1)
S FCP I10FC(i) + 100 ≤ S FCP I10FC(i + 1)
S FCP P10FC(i) + 100 ≤ S FCP P10FC(i + 1)
S FCP O10FC(i) + 100 ≤ S FCP O10FC(i + 1)

INDUSTRIAL EXAMPLE: NASA X-38 CREW RETURN VEHICLE 171
S ICP I10FC CMDS(i) + 100 ≤ S ICP I10FC CMDS(i + 1)
S ICP I10FC SENSOR(i + 1) − 100 ≤ S ICP I10FC SENSOR(i)
S FCP I10FC(i + 1) − 100 ≤ S FCP I10FC(i)
S FCP P10FC(i + 1) − 100 ≤ S FCP P10FC(i)
S FCP O10FC(i + 1) − 100 ≤ S FCP O10FC(i)
S ICP I10FC CMDS(i + 1) − 100 ≤ S ICP I10FC CMDS(i)
; 50 Hz NFC tasks
S ICP I50NFC SENSOR(i) + 20 ≤ S ICP I50NFC SENSOR(i + 1)
S FCP I50NFC(i) + 20 ≤ S FCP I50NFC(i + 1)
S FCP P50NFC(i) + 20 ≤ S FCP P50NFC(i + 1)
S ICP I50NFC SENSOR(i + 1) − 20 ≤ S ICP I50NFC SENSOR(i)
S FCP I50NFC(i + 1) − 20 ≤ S FCP I50NFC(i)
S FCP P50NFC(i + 1) − 20 ≤ S FCP P50NFC(i)
Priority assertions:
EFCP I50FC(i) ≤ S FCP I10FC(i)
;50 Hz FC higher priority than 10 Hz FC
EFCP I50FC(i) ≤ S FCP I50NFC(i)
;50 Hz FC higher priority than 50 Hz NFC Negation of safety assertion:
SICP I50FC SENSOR(I ) + 11 ≤ E ICP I50FC CMDS(I)
SICP I10FC SENSOR(I ) + 51 ≤ E ICP I10FC CMDS(I)
6.7.6Constraint Graph Analysis
To verify the satisfaction of the safety assertion, the Presburger formulas are represented in a constraint graph shown in [Rice and Cheng, 1999]. The system specification alone produces a graph with no positive cycles. Negation of the safety assertion, however, yields edges that produce positive cycles between clusters, thus it verifies critical system performance. For example, a positive cycle with vertices S ICP I50FC SENSOR, E ICP I50FC CMDS, S ICP I50FC CMDS, S FCP O50FC, S FCP P50FC, S FCP I50FC, and back to S ICP I50FC SENSOR, yields a cycle with weight 1.