Chapter 4

Programmer’s Model for Test

This chapter describes the additional logic for functional verification and production testing. It contains the following sections:

•PrimeCell SSPMS test harness overview on page 4-2

•Scan testing on page 4-4

•Test registers on page 4-5.

Programmer’s Model for Test

4.1PrimeCell SSPMS test harness overview

The additional logic for functional verification and production testing allows:

•generation of an internal test clock enable (ClkEnable) signal based on the contents of the SSPTCR register

•generation of internal test resets (nRES, nSSPRES) based on the contents of the SSPTCR register and the level on the SCANMODE pin

•provision of a write interface for the test registers

•provision of test input stimulus multiplexing for non-AMBA inputs.

The PrimeCell SSPMS can be configured to a test mode in which the serial clock rate counter is bypassed when selected, and the external clock input is used as the transmit/ receive clock. These test features are controlled by test registers. This allows testing of the PrimeCell SSPMS in isolation from the rest of the system using only transfers from the AMBA APB.

Off-chip test vectors are supplied through a 32-bit parallel External Bus Interface (EBI) and converted to internal AMBA bus transfers. The application of test vectors is controlled through the Test Interface Controller (TIC) AMBA bus master module.

During test, the SSPCLK signal must be driven by the free-running PCLK clock signal so that the test vectors can be frequency independent. This clock multiplexing must be performed externally from the PrimeCell SSPMS. Figure 4-1 shows the PrimeCell SSPMS test harness.

Figure 4-1 PrimeCell SSPMS test harness

Programmer’s Model for Test

All clocked elements in the PrimeCell SSPMS have a clock enable control input, ClkEnable. To facilitate testing of the PrimeCell SSPMS, an internal ClkEnable is generated in a controlled manner in the test mode. In the normal mode, the ClkEnable signal is pulled continuously HIGH. If the TESTEN bit in the SSPTCR register is set, the device is said to be in the test mode. In the test mode, if the TESTCLKEN bit in the SSPTCR register is not set, then ClkEnable is pulled HIGH. Otherwise, the internal test clock enable is selected based on the REGCLK bit value. If REGCLK is set, then a pulse on the ClkEnable line is generated only on accesses to the SSPTCER register address, that is when the internal SSPTCERSel signal is asserted. If the REGCLK bit is not set, then a clock enable is generated on every access to the device. The ClkEnable signal is generated with PENABLE and PSEL as gating terms.

When the TESTRST bit in the SSPTCR register is set, the asynchronous reset input to all the clocked elements in the design is pulled LOW continuously. When the SCANMODE pin is LOW, the test reset generated by ORing the external reset with the test reset is driven as the internal reset (nRES for PCLK-domain logic and nSSPRES for SSPCLK-domain logic). When SCANMODE is HIGH, the test reset does not have any effect and the external resets BnRES and nSSPRST are driven on the internal reset lines.

Therefore when SCANMODE is 0, the internal nRES signal is pulled LOW whenever BnRES is LOW, or when the TESTRST bit in the SSPTCR is set. Similarly, when SCANMODE is 0, the internal nSSPRES signal is pulled LOW whenever nSSPRST is LOW, or when the TESTRST bit in the SSPTCR register is set.

When SCANMODE is 1, nRES is pulled LOW only when BnRES is asserted. Similarly, when SCANMODE is 1, nSSPRES is pulled LOW only when nSSPRST is asserted.

The test registers themselves are not affected by test reset.

When the TESTINPSEL bit in the SSPTCR register is set, the non-AMBA inputs SSPRXD and SFRMIN are multiplexed with the corresponding bits in the SSPTISR register.

Programmer’s Model for Test

4.2Scan testing

The PrimeCell SSPMS peripheral has been designed to simplify the insertion of scan test cells and the use of Automatic Test Pattern Generation (ATPG) for an alternative method of manufacturing test.

During scan testing, the SCANMODE input must be driven HIGH to ensure that all internal data storage elements can be asynchronously reset. For normal use and application of manufacturing test vectors through the TIC, SCANMODE must be driven LOW.