ARM PrimeCell Synchronous Serial Port Master and Slave (PL021) Signal Descriptions
A.1 AMBA APB signals
The PrimeCell SSPMS module is connected to the AMBA APB as a bus slave.
Table A-1 describes the APB signals that are used and produced.
Table A-1 AMBA APB signal descriptions
Name |
Type |
Source/ |
Description |
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destination |
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BnRES |
Input |
Reset controller |
Bus reset signal, active LOW. |
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PADDRH[7:6] |
Input |
APB bridge |
Subset of AMBA APB address bus. |
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PADDRL[4:2] |
Input |
APB bridge |
Subset of AMBA APB address bus. |
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PCLK |
Input |
Clock generator |
AMBA APB clock, used to time all bus |
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transfers. |
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PENABLE |
Input |
APB bridge |
AMBA APB enable signal. PENABLE |
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is asserted HIGH for one cycle of PCLK |
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to enable a bus transfer. |
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PRDATA [15:0] |
Output |
APB bridge |
Unidirectional AMBA APB read data |
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bus. |
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PSEL |
Input |
APB bridge |
PrimeCell SSPMS select signal from |
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decoder. When set to 1 this signal |
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indicates the slave device is selected by |
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the AMBA APB bridge, and that a data |
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transfer is required. |
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PWDATA [15:0] |
Input |
APB bridge |
Unidirectional AMBA APB write data |
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bus. |
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PWRITE |
Input |
APB bridge |
AMBA APB transfer direction signal, |
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indicates a write access when HIGH, |
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read access when LOW. |
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A-2 |
Copyright © ARM Limited 1999. All rights reserved. |
ARM DDI 0171B |
ARM PrimeCell Synchronous Serial Port Master and Slave (PL021) Signal Descriptions
A.2 On-chip signals
Table A-2 shows the non-AMBA signals from the block.
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Table A-2 On-chip signals |
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Name |
Type |
Source/ |
Description |
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destination |
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SSPCLK |
Input |
Clock |
Main PrimeCell SSPMS clock input. |
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generator |
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nSSPRST |
Input |
Reset |
PrimeCell SSPMS reset signal to |
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controller |
SSPCLK clock domain, active LOW. |
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The reset controller must use BnRES |
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to assert nSSPRST asynchronously, |
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but negate it synchronously with |
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SSPCLK. |
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SSPTXINTR |
Output |
Interrupt |
Transmit FIFO service request. |
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controller |
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SSPRXINTR |
Output |
Interrupt |
Receive FIFO service request. |
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controller |
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SSPRORINTR |
Output |
Interrupt |
PrimeCell SSPMS receive overrun |
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controller |
interrupt. |
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SSPINTR |
Output |
Interrupt |
PrimeCell SSPMS interrupt. This |
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controller |
interrupt is an OR of the three |
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individual interrupts SSPTXINTR, |
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SSPRXINTR and SSPRORINTR. |
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SCANMODE |
Input |
Test controller |
PrimeCell SSPMS scan test hold |
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input. This signal must be asserted |
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HIGH during scan testing to ensure |
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that internal data storage elements |
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can be asynchronously reset. |
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SCANMODE must be negated LOW |
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during normal use or when applying |
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manufacturing test vectors through |
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the TIC. |
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SCANENABLE |
Input |
Test controller |
Place holder for scan path select |
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signal. |
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SCANINPCLK |
Input |
Test controller |
Place holder for scan data input signal |
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(PCLK domain). |
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ARM DDI 0171B |
Copyright © ARM Limited 1999. All rights reserved. |
A-3 |
ARM PrimeCell Synchronous Serial Port Master and Slave (PL021) Signal Descriptions
Table A-2 On-chip signals (continued)
Name |
Type |
Source/ |
Description |
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destination |
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SCANOUTPCLK |
Output |
Test controller |
Place holder for scan data output |
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signal (PCLK domain). |
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SCANINSSPCLK |
Input |
Test controller |
Place holder for scan data input signal |
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(SSPCLK domain). |
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SCANOUTSSPCLK |
Output |
Test controller |
Place holder for scan data output |
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signal (SSPCLK domain). |
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A-4 |
Copyright © ARM Limited 1999. All rights reserved. |
ARM DDI 0171B |
ARM PrimeCell Synchronous Serial Port Master and Slave (PL021) Signal Descriptions
A.3 Signals to pads
Table A-3 describes the signals from the PrimeCell SSPMS to input/output pads of the chip. It is the responsibility of the user to make proper use of the peripheral pins to meet the exact interface requirements.
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Table A-3 Pad signal descriptions |
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Name |
Type |
Source/ |
Description |
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destination |
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SFRMOUT |
Output |
Pad |
PrimeCell SSPMS serial frame output (master). |
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SCLKOUT |
Output |
Pad |
PrimeCell SSPMS serial clock output (master). |
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SSPRXD |
Input |
Pad |
PrimeCell SSPMS serial data input. |
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SSPTXD |
Output |
Pad |
PrimeCell SSPMS serial data output. |
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SSPCTLOE |
Output |
Pad |
Output enable signal for SCLKOUT and |
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SFRMOUT outputs from the PrimeCell SSPMS. |
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This output is set when the device is in master |
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mode and cleared when the device is in slave |
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mode. |
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SFRMIN |
Input |
Pad |
PrimeCell SSPMS serial frame input (slave). |
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SCLKIN |
Input |
Pad |
PrimeCell SSPMS serial clock input (slave). |
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SSPOE |
Output |
Pad |
Output enable signal to indicate when SSPTXD |
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is valid. |
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|
ARM DDI 0171B |
Copyright © ARM Limited 1999. All rights reserved. |
A-5 |
ARM PrimeCell Synchronous Serial Port Master and Slave (PL021) Signal Descriptions
A-6 |
Copyright © ARM Limited 1999. All rights reserved. |
ARM DDI 0171B |
Index
The items in this index are listed in alphabetic order, with symbols and numerics appearing at the end. The references given are to page numbers.
A |
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F |
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Interrupts |
3-10 |
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AMBA |
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Features |
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L |
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APB interface |
2-4 |
Microwire |
1-4 |
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AMBA compatibility |
1-5 |
PrimeCell SSP |
1-2 |
Little-endian |
1-5 |
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SPI 1-3 |
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B |
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TI SSI |
1-4 |
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M |
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FIFO |
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Big-endian 1-5 |
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receive |
2-4 |
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Microwire |
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2-9 |
transmit |
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2-4 |
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1-4 |
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Bit rate generation |
Frame format |
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2-10 |
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features |
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frame format 2-17 |
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Microwire |
2-17 |
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C |
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Motorola |
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Motorola SPI 2-12 |
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TI SSI |
2-11 |
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SPI frame format |
2-12 |
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Clock prescale register |
3-8 |
Functional description |
2-3 |
N |
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Clock prescaler |
2-4 |
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I |
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Compatibility,AMBA |
1-5 |
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National Semiconductor |
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Control register |
3-4, 3-5 |
Input generation logic |
2-5 |
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Microwire |
2-17 |
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nibmode |
4-7 |
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D |
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Interface reset |
2-7 |
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Interrupt clear register |
3-9 |
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Data register 3-7 |
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Interrupt identification register |
3-9 |
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||||
ARM DDI 0171B |
Copyright © ARM Limited 1999. All rights reserved. |
Index-i |
Index
P
PrimeCell SSP |
|
features |
1-2 |
PrimeCell SSP operation 2-7 |
|
Programmer’s model 3-1 |
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for test |
4-1 |
R
Receive FIFO |
2-4 |
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REGCLK |
4-6 |
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Register |
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clock prescale |
3-8 |
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control 3-4, 3-5 |
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data |
3-7 |
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descriptions |
3-4 |
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interrupt clear |
3-9 |
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interrupt identification 3-9 |
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status |
3-7 |
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test |
4-5 |
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test clock enable |
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4-5 |
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test clock pre-scale counter 4-9 |
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test control |
4-6 |
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test input stimulus |
4-8 |
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test mode |
4-7 |
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test output capture |
4-8 |
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Register block |
2-4 |
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Registered clock mode |
4-6 |
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S
Scan testing |
|
4-4 |
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SCLK |
4-9 |
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SFRM |
4-9 |
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SPI features |
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1-3 |
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SSP |
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register descriptions |
3-4 |
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register summary 3-3 |
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SSPCPSC |
4-9 |
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SSPINTR |
3-11, 4-8 |
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SSPOE |
4-8 |
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SSPORINTR |
3-11 |
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SSPRXD |
|
4-8 |
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SSPRXINTR |
3-10 |
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SSPTXD |
|
4-9 |
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SSPTXINTR |
3-10 |
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Status register |
3-7 |
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Summary of SSP registers |
3-3 |
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Synchronizing registers and logic 2-6
T
Test clock |
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enable |
4-6 |
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enable register |
4-5 |
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pre-scale counter register |
4-9 |
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Test control register |
4-6 |
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Test harness |
|
4-2 |
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Test input |
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select |
4-6 |
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stimulus register |
4-8 |
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Test mode |
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enable |
4-7 |
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register |
|
4-7 |
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Test output capture register |
4-8 |
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Test registers |
4-5 |
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and logic |
2-6 |
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Test reset |
4-6 |
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TESTCLKEN |
4-6 |
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TESTEN |
4-7 |
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Testing, scan |
4-4 |
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TESTINPSEL |
4-6 |
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TESTRST |
4-6 |
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Texas Instruments |
2-11 |
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TI SSI |
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features |
|
1-4 |
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frame format 2-11 |
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Transmit FIFO |
2-4 |
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Transmit/receive logic 2-5 |
|
|||
Index-ii |
Copyright © ARM Limited 1999. All rights reserved. |
ARM DDI 0171B |