Programmer’s Model

3.4Interrupts

There are four interrupts generated by the PrimeCell SSPMS. Three of these are individual, maskable, active HIGH interrupts:

•SSPRXINTR - SSP receive FIFO service interrupt request

•SSPTXINTR - SSP transmit FIFO service interrupt request

•SSPRORINTR - SSP receive overrun interrupt request.

The fourth is a combined single interrupt SSPINTR.

Each of the three individual maskable interrupts may be enabled or disabled by changing the mask bits in SSPCR1. Setting the appropriate mask bit HIGH enables the interrupt.

Provision of the individual outputs as well as a combined interrupt output, allows use of either a global interrupt service routine, or modular device drivers to handle interrupts.

The transmit and receive dataflow interrupts SSPTXINTR and SSPRXINTR have been separated from the status interrupts to allow use in a DMA controller, so that data can be read or written in response to just the FIFO trigger levels.

The status of the individual interrupt sources can be read from SSPIIR.

3.4.1SSPRXINTR

The receive interrupt is asserted when there are four or more valid entries in the receive FIFO.

3.4.2SSPTXINTR

The transmit interrupt is asserted when the FIFO is less than or equal to half full (when there is space for four or more entries).

The transmitter interrupt SSPTXINTR is not qualified with the PrimeCell SSPMS enable signal, which allows operation in one of two ways. Data can be written to the transmit FIFO prior to enabling the PrimeCell SSPMS and the interrupts. Alternatively, the PrimeCell SSPMS and interrupts can be enabled so that data can be written to the transmit FIFO by an interrupt service routine.

Programmer’s Model

3.4.3SSPRORINTR

The receive overrun interrupt SSPORINTR is asserted when the FIFO is already full and an additional data frame is received, causing an overrun of the FIFO. Data is overwritten in the shift register, but not the FIFO.

3.4.4SSPINTR

The interrupts are also combined into a single output (SSPINTR) which is an OR function of the individual masked sources. This output can be connected to the system interrupt controller to provide another level of masking on an individual per-peripheral basis.

The combined PrimeCell SSPMS interrupt is asserted if any of the three individual interrupts above are asserted and enabled.

Programmer’s Model