Programmer’s Model for Test
4.3Test registers
The PrimeCell SSPMS test registers are memory-mapped as shown in Table 4-1.
Table 4-1 Test registers memory map
Address |
Type |
Width |
Reset value |
Name |
Description |
|
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|
|
|
|
SSP Base + 0x40–0x7c |
Read/write |
0 |
- |
SSPTCER |
Test clock enable register. |
|
|
|
|
|
|
SSP Base + 0x80 |
Read/write |
5 |
0x00 |
SSPTCR |
Test control register. |
|
|
|
|
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|
SSP Base + 0x84 |
Read/write |
2 |
0x00 |
SSPTMR |
Test mode register. |
|
|
|
|
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|
SSP Base + 0x88 |
Read/write |
3 |
0x00 |
SSPTISR |
Test input stimulus |
|
|
|
|
|
register. |
|
|
|
|
|
|
SSP Base + 0x8c |
Read |
6 |
0x00 |
SSPTOCR |
Test output capture |
|
|
|
|
|
register. |
|
|
|
|
|
|
SSP Base + 0x90 |
Read |
7 |
0x00 |
SSPTCPCR |
Test clock prescale counter |
|
|
|
|
|
register. |
|
|
|
|
|
|
Each register shown in Table 4-1 is described below.
4.3.1SSPTCER [0] (+0x40–0x7c)
SSPTCER is the test clock enable register and is a 0-bit register. Table 4-2 shows the bit assignments for the SSPTCER.
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|
Table 4-2 SSPTCER register |
|
|
|
Bit |
Name |
Description |
|
|
|
15:0 |
- |
When in registered clock mode (refer to SSPTCR [5] (+0x80) on |
|
|
page 4-6), a test clock enable is produced only when this register is |
|
|
accessed (read or write). |
|
|
|
SSPTCER has a multiple word space in the register address map to allow for the generation of multiple test clock enable pulses.
ARM DDI 0171B |
Copyright © ARM Limited 1999. All rights reserved. |
4-5 |
Programmer’s Model for Test
4.3.2SSPTCR [5] (+0x80)
SSPTCR is the test control register. This general test register controls operation of the PrimeCell SSPMS under test conditions. Table 4-3 shows the bit assignments for the SSPTCR.
|
|
Table 4-3 SSPTCR register |
|
|
|
Bit |
Name |
Description |
|
|
|
15:5 |
- |
Reserved, read unpredictable, should be written as 0. |
|
|
|
4 |
Test Input Select |
By default, this bit is cleared to 0 for normal operation. This |
|
(TESTINPSEL) |
bit selects the source for the internal input signal for external |
|
|
non-AMBA inputs. |
|
|
When this bit is cleared to 0, the primary inputs are taken |
|
|
from the external pads (normal operation). |
|
|
When this bit is set to 1, the values programmed in SSPTISR |
|
|
are used to drive the internal line. |
|
|
|
3 |
Test Reset |
By default, this bit is cleared to 0 for normal operation when |
|
(TESTRST) |
reset by BnRES. |
|
|
When this bit is set to 1, a reset is asserted throughout the |
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|
module, EXCEPT for the test registers (this simulates reset by |
|
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BnRES being asserted to 0). |
|
|
|
2 |
Registered Clock |
This bit selects the internal test clock mode: |
|
Mode |
0 = Strobe clock mode is selected which generates a test clock |
|
(REGCLK) |
enable on every AMBA APB access (read or write) to the |
|
|
block. Use of strobe clock mode allows testing with less test |
|
|
vectors when testing functions such as counters. The Test |
|
|
Clock Enable is generated from PENABLE ANDed with |
|
|
PSEL. |
|
|
1 = Registered clock mode is selected which only generates a |
|
|
test clock enable on an APB access to the SSPTCER (SSP |
|
|
Test Clock Enable register) location. |
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|
This bit has no effect unless bit 0 and bit 1 are both set to 1. |
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|
This bit is cleared to 0 by default on reset by BnRES. |
|
|
|
1 |
Test Clock Enable |
This bit selects the source of the test clock: |
|
(TESTCLKEN) |
0 = Internal clock enable is continuously HIGH. |
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|
1 = Internal test clock enable is selected, so that the test |
|
|
clocks are enabled for only one period of the input clock per |
|
|
APB access. The internal clock enable mode depends on the |
setting of bit 2.
This bit has no effect unless bit 0 is set to 1.
This bit is cleared to 0 by default on reset by BnRES.
4-6 |
Copyright © ARM Limited 1999. All rights reserved. |
ARM DDI 0171B |
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Programmer’s Model for Test |
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Table 4-3 SSPTCR register (continued) |
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|
|
|
Bit |
Name |
Description |
|
|
|
|
|
0 |
Test Mode Enable |
0 |
= Normal operating mode is selected. |
|
(TESTEN) |
1 |
= Test mode is selected. |
|
|
Bits 1 and 2 have no effect unless bit 0 is set to 1. |
|
|
|
This bit is cleared to 0 by default on reset by BnRES. |
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|
|
|
|
4.3.3SSPTMR [1] (+0x84)
SSPTMR is the test mode register and controls the specific test modes for the PrimeCell SSPMS. Table 4-4 shows the bit assignments for the SSPTMR.
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|
Table 4-4 SSPTMR register |
|
|
|
Bit |
Name |
Description |
|
|
|
15:2 |
- |
Reserved, read unpredictable, should be written as 0. |
|
|
|
1 |
CPSCNIBMODE |
When set, the 7-bit CPSC prescale counter is partitioned into |
|
|
two nibbles (3, 4), and decrements by 0x11 on successive |
|
|
clocks. |
|
|
|
0 |
nibmode |
When set, the 8-bit SCR counter is partitioned into two nibbles, |
|
|
and decrements by 0x11 on successive clocks. |
|
|
|
Note
The test registers must not be accessed during normal operation.
4.3.4SSPTISR [1] (+0x88)
SSPTISMR is the test input stimulus register and provides test mode stimulus for the SSPRXD, SFRMIN and SCLKIN inputs to the PrimeCell SSPMS. When the TESTINPSEL bit in the SSPTCR register is 1, the values in the SSTISR register are routed to the internal lines. Table 4-5 shows the bit assignments for the SSPTISR.
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|
Table 4-5 SSPTISR register |
|
|
|
Bit |
Name |
Description |
|
|
|
15:3 |
- |
Reserved, read unpredictable, should be written as 0. |
|
|
|
2 |
SCLKIN |
Read/write. Test data input for the SCLKIN pin. |
|
|
|
ARM DDI 0171B |
Copyright © ARM Limited 1999. All rights reserved. |
4-7 |
Programmer’s Model for Test
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Table 4-5 SSPTISR register |
|
|
|
Bit |
Name |
Description |
|
|
|
1 |
SFRMIN |
Read/write. Test data input for the SFRMIN pin. |
|
|
|
0 |
SSPRXD |
Read/write. Test data input for the SSPRXD pin. |
|
|
|
4.3.5SSPTOCR [6] (+0x8c)
SSPTOCR is the test output capture register (read-only). This register provides observation of the primary outputs of the PrimeCell SSPMS. The SSPINTR interrupt is an OR of the three individual interrupts SSPRXINTR, SSPTXINTR and SSPRORINTR. Table 4-6 shows the bit assignments for the SSPTOCR.
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|
|
Table 4-6 SSPTOCR register |
|
|
|
|
Bit |
Name |
Description |
|
|
|
|
|
15:6 |
- |
Reserved, read unpredictable, should be written as 0. |
|
|
|
|
|
5 |
SSPCTLOE |
Read-only. This bit returns the status of the SSPCTLOE output |
|
|
|
signal from the PrimeCell SSPMS. |
|
|
|
0 |
= SSPCTLOE is driven to logic 0. |
|
|
1 |
= SSPCTLOE is driven to logic 1. |
|
|
|
|
4 |
SSPINTR |
Read-only. This bit returns the status of the SSPINTR output signal |
|
|
|
from the PrimeCell SSPMS. The SSPINTR interrupt is an OR of the |
|
|
|
three individual interrupts SSPTXINTR, SSPRXINTR and |
|
|
|
SSPRORINTR. |
|
|
|
0 |
= SSPINTR is not asserted. |
|
|
1 |
= SSPINTR is asserted. |
|
|
|
|
3 |
SSPOE |
Read-only. This bit returns the status of the SSPOE output signal |
|
|
|
from the PrimeCell SSPMS. |
|
|
|
0 |
= SSPOE is driven to logic 0. |
|
|
1 |
= SSPOE is driven to logic 1. |
|
|
|
|
2 |
SSPTXD |
Read-only. This bit returns the status of the SSPTXD output signal |
|
|
|
from the PrimeCell SSPMS. |
|
|
|
0 |
= SSPTXD is driven to logic 0. |
|
|
1 |
= SSPTXD is driven to logic 1. |
|
|
|
|
4-8 |
Copyright © ARM Limited 1999. All rights reserved. |
ARM DDI 0171B |
|
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|
Programmer’s Model for Test |
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Table 4-6 SSPTOCR register (continued) |
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|
|
|
Bit |
Name |
Description |
|
|
|
|
|
1 |
SCLKOUT |
Read-only. This bit returns the status of the SCLKOUT output |
|
|
|
signal from the PrimeCell SSPMS. The reset value of this output is |
|
|
|
0, because the reset value of FRF[1:0] indicates that the frame |
|
|
|
format is Motorola SPI and the reset value of SPO is 0. For this |
|
|
|
combination, the inactive SCLKOUT value is 0. |
|
|
|
0 |
= SCLKOUT is driven to logic 0. |
|
|
1 |
= SCLKOUT is driven to logic 1. |
|
|
|
|
0 |
SFRMOUT |
Read-only. This bit returns the status of the SFRMOUT output |
|
|
|
signal from the PrimeCell SSPMS. The reset value of this output is |
|
|
|
1, because the reset value of FRF[1:0] indicates that the frame |
|
|
|
format is Motorola SPI, for which the inactive SFRMOUT value |
|
|
|
is 1. |
|
|
|
0 |
= SFRMOUT is driven to logic 0. |
|
|
1 |
= SFRMOUT is driven to logic 1. |
|
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|
4.3.6SSPTCPCR [7] (+0x90)
SSPTCPCR is the test clock prescale counter register (read-only). This register provides observation for the clock prescale counter. The counter is a 7-bit, free-running, down counter that operates on SSPCLK, in normal mode of operation. It can be configured as two nibbles and decremented by test clocks in test mode through the SSPTMR and SSPTCR registers.The seven most significant bits programmed in the 8-bit SSPCPSR register form the reload value for this counter. The counter reloads when it reaches 1. Thus the reload value for the counter is one half of the even-numbered value written into the SSPCPSR register. Table 4-7 shows the bit assignments for the SSPTCPCR.
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|
Table 4-7 SSPTCPCR register |
|
|
|
Bit |
Name |
Description |
|
|
|
15:7 |
- |
Reserved, read unpredictable, should be written as 0. |
|
|
|
6:0 |
SSPCPSC |
Read-only. This bit returns the current count of the clock prescale |
|
|
counter. |
|
|
|
ARM DDI 0171B |
Copyright © ARM Limited 1999. All rights reserved. |
4-9 |
Programmer’s Model for Test
4-10 |
Copyright © ARM Limited 1999. All rights reserved. |
ARM DDI 0171B |
Appendix A
ARM PrimeCell Synchronous Serial Port Master
and Slave (PL021) Signal Descriptions
This appendix describes the signals that interface with the ARM PrimeCell Synchronous Serial Port Master and Slave (PL021). It contains the following sections:
•AMBA APB signals on page A-2
•On-chip signals on page A-3
•Signals to pads on page A-5.
ARM DDI 0171B |
Copyright © ARM Limited 1999. All rights reserved. |
A-1 |