Functional Overview

2.1ARM PrimeCell SDRAM Controller (PL170) overview

Figure 2-1 shows the top-level hierarchy of the PrimeCell SDRAM Controller.

Figure 2-1 PrimeCell SDRAM Controller top level hierarchy

A minimum system comprises:

•PrimeCell SDRAM control engine

•Main AHB interface on page 2-3

•Pad interface on page 2-6

•Additional AHB ports on page 2-6.

Note

The additional AHB ports are optional, and can be included or omitted depending on the particular system requirements.

2.1.1PrimeCell SDRAM control engine

The PrimeCell SDRAM control engine arbitrates between the access requests from the four AHB ports (connected to the main bus and DMA interfaces). As a result it generates a sequence of commands and issues these to the SDRAMs to transfer the requested data.