Добавил:
Andrey
Опубликованный материал нарушает ваши авторские права? Сообщите нам.
Вуз:
Предмет:
Файл:ARM PrimeCell SDRAM controller technical reference manual.pdf
X
- •Preface
- •About this document
- •Intended audience
- •Organization
- •Typographical conventions
- •Timing diagram conventions
- •Further reading
- •ARM publications
- •Feedback
- •Feedback on this document
- •Feedback on the ARM PrimeCell SDRAM Controller
- •Introduction
- •1.1 About the ARM PrimeCell SDRAM Controller (PL170)
- •1.1.1 General information
- •1.1.2 Features of the PrimeCell SDRAM Controller
- •Functional Overview
- •2.1 ARM PrimeCell SDRAM Controller (PL170) overview
- •2.1.1 PrimeCell SDRAM control engine
- •Arbitration
- •2.1.2 Main AHB interface
- •Control registers
- •2.1.3 Optional features
- •Merging write buffer
- •Read buffer
- •2.1.4 Additional AHB ports
- •2.1.5 Pad interface
- •2.2 Overview of a Primecell SDRAM, ASIC/ASSP, unified memory system
- •2.2.1 External bus
- •2.2.2 Internal bus
- •Multi-port access
- •Clock domains
- •Maintaining memory during low-power sleep modes
- •2.2.4 Example signal waveforms
- •Programmer’s Model
- •3.1 About the programmer’s model
- •3.2 Summary of PrimeCell SDRAM Controller registers
- •3.3 Register descriptions
- •3.3.1 Configuration registers
- •Configuration register 0
- •Configuration register 1
- •3.3.2 Refresh timer register
- •3.4 System initialization
- •3.5 Address mapping
- •3.5.1 Remapping the AMBA address to the SDRAM address bus
- •A.1 On-chip signals
- •A.1.1 AMBA AHB signals
- •A.1.2 Miscellaneous
- •A.2 Off-chip signals
- •A.2.1 SDRAM memory interface signals
- •First group
- •Second group
- •Third group
- •B.1 Commands
Programmer’s Model
3.5.1Remapping the AMBA address to the SDRAM address bus
The mapping presented in the previous section should satisfy the following two constraints:
•memory selected by each chip select should be contiguous
•the bank address should be changed on the page address for SDRAM.
3-14 |
Copyright © ARM Limited 1999-2001. All rights reserved. |
ARM DDI 0159D |
Appendix A
ARM PrimeCell SDRAM Controller (PL170)
Signal Descriptions
This appendix describes the signals that interface with the ARM PrimeCell
SDRAM Controller (PL170). It contains the following sections:
•On-chip signals on page A-2
•Off-chip signals on page A-5.
ARM DDI 0159D |
Copyright © ARM Limited 1999-2001. All rights reserved. |
A-1 |
Соседние файлы в предмете Электротехника