About this document

This document is the technical reference manual for the ARM PrimeCell SDRAM

Controller.

Intended audience

This document has been written for implementation engineers and architects, and provides a description of an optimal SDRAM controller architecture. The PrimeCell SDRAM Controller aims to help designers integrate high performance, low power, SDRAM into a design as quickly as possible.

Organization

This document is organized into the following chapters:

Chapter 1 Introduction

Read this chapter for an introduction to the PrimeCell SDRAM (SDRAM)

Controller.

Chapter 2 Functional Overview

Read this chapter for an overview of the PrimeCell SDRAM Controller in a unified memory system.

Chapter 3 Programmer’s Model

Read this chapter for a description of the registers and for details of system initialization.

Appendix A ARM PrimeCell SDRAM Controller (PL170) Signal Descriptions

Read this appendix for a description of the PrimeCell SDRAM Controller signals.

Appendix B Appendix B ARM PrimeCell SDRAM Controller (PL170) Command

Descriptions

Read this appendix for a description of the PrimeCell SDRAM Controller commands.

Typographical conventions

The following typographical conventions are used in this document:

typewriter italic

Denotes arguments to commands or functions where the argument is to be replaced by a specific value.

typewriter bold

Denotes language keywords when used outside example code.

Timing diagram conventions

This manual contains one or more timing diagrams. The following key explains the components used in these diagrams. Any variations are clearly labeled when they occur. Therefore, no additional meaning should be attached unless specifically stated.

Clock

HIGH to LOW

Transient

HIGH/LOW to HIGH

Bus stable

Bus to high impedance

Bus change

High impedance to stable bus

Key to timing diagram conventions

Shaded bus and signal areas are undefined, so the bus or signal can assume any value within the shaded area at that time. The actual level is unimportant and does not affect normal operation.