Functional Overview

Maintaining memory during low-power sleep modes

In many systems, the contents of the memory system needs to be maintained during low-power sleep modes. To aid the design of this class of system, two features are provided in the PrimeCell SDRAM Controller:

•SDRAM refresh over soft reset

•a mechanism to place the SDRAMs into self-refresh mode.

The above features enable interaction with a system controller, which will typically be present to control the safe transition between power-up, reset, normal, and sleep modes. The associated control signals can be tied off if not required.

2.2.4Example signal waveforms

This section contains figures which show the general sequence of signal transitions for write and read transfers. In these examples, the access is to an open SDRAM page.

Functional Overview

Figure 2-5 shows a second PrimeCell SDRAM Controller write example (delayed

ExtBusGnt signal).

Figure 2-5 PrimeCell SDRAM Controller write example

Functional Overview

Figure 2-6 shows a PrimeCell SDRAM Controller read example.

HCLK

HSELram

HWRITE

Read3

Read

XferOut3

EndOfXfer3

ExtBusReq

ExtBusGnt

Figure 2-6 PrimeCell SDRAM Controller read example

Functional Overview