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- •Preface
- •About this document
- •Intended audience
- •Organization
- •Typographical conventions
- •Timing diagram conventions
- •Further reading
- •ARM publications
- •Feedback
- •Feedback on this document
- •Introduction
- •1.2 AMBA compatibility
- •Functional Overview
- •2.2.1 AMBA APB interface
- •2.2.2 Control logic
- •2.2.3 Drive output logic
- •2.2.4 Synchronizing registers and logic
- •2.2.5 Test registers and logic
- •2.3.1 Interface reset
- •2.3.2 Clock signals
- •Programmer’s Model
- •3.1 About the programmer’s model
- •3.3 Register descriptions
- •3.3.1 PMPCON0 [8] (+0x00)
- •3.3.2 PMPCON1 [8] (+0x04)
- •3.3.3 PMPFREQ [8] (+0x08)
- •Programmer’s Model for Test
- •4.2 Scan testing
- •4.3 Test registers
- •4.3.2 PMPTCR [5] (+0x80)
- •4.3.3 PMPTMR [2] (+0x84)
- •4.3.4 PMPTISR [6] (+0x88)
- •4.3.5 PMPTOCR [3] (+0x8c)
- •4.3.6 PMPFC0 [5] (+0x90)
- •4.3.7 PMPFC1 [5] (+0x98)
- •4.3.8 PMPDRVCNT [8] (+0xa0)
- •A.1 AMBA APB signals
- •A.2 On-chip signals
- •A.3 Signals to pads
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Chapter 3
Programmer’s Model
This chapter describes the ARM PrimeCell DC-DC Converter Interface (PL160) registers and provides details needed when programming the microcontroller. It contains the following sections:
•About the programmer’s model on page 3-2
•Summary of PrimeCell DC-DC Converter Interface registers on page 3-3
•Register descriptions on page 3-4.
ARM DDI 0147D |
© Copyright ARM Limited 1999. All rights reserved. |
3-1 |
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Programmer’s Model
3.1About the programmer’s model
The base address of the PrimeCell DC-DC Converter Interface is not fixed and may be different for any particular system implementation. However, the offset of any particular register from the base address is fixed.
The following locations are reserved, and must not be used during normal operation:
•locations at offsets +0x0c through +0x3c and 0xa4 through 0xff are reserved for possible future extensions
•locations at offsets 0x40 through 0xa0 are reserved for test purposes.
3-2 |
© Copyright ARM Limited 1999. All rights reserved. |
ARM DDI 0147D |
![](/html/616/253/html_crHd4GIe6r.s1w5/htmlconvd-OPljMF27x1.jpg)
Programmer’s Model
3.2Summary of PrimeCell DC-DC Converter Interface registers
The PrimeCell DC-DC Converter Interface registers are shown in Table 3-1.
Table 3-1 PrimeCell DC-DC Converter Interface register summary
Address |
Type |
Width |
Reset |
Name |
Description |
|
value |
||||||
|
|
|
|
|
||
|
|
|
|
|
|
|
DCDCBase + |
Read/ |
8 |
0x00 |
PMPCON0 |
Drive 0 configuration |
|
0x00 |
write |
|
|
|
register. |
|
|
|
|
|
|
|
|
DCDCBase + |
Read/ |
8 |
0x00 |
PMPCON1 |
Drive 1 configuration |
|
0x04 |
write |
|
|
|
register. |
|
|
|
|
|
|
|
|
DCDCBase + |
Read/ |
8 |
0x00 |
PMPFREQ |
Frequency |
|
0x08 |
write |
|
|
|
configuration register. |
|
|
|
|
|
|
|
|
DCDCBase + |
- |
- |
- |
- |
Reserved. |
|
0x0c-3c |
|
|
|
|
|
|
|
|
|
|
|
|
|
DCDCBase + |
- |
- |
- |
- |
Reserved (for test |
|
0x40-a0 |
|
|
|
|
purposes). |
|
|
|
|
|
|
|
|
DCDCBase + |
- |
- |
- |
- |
Reserved. |
|
0xa4-ff |
|
|
|
|
|
|
|
|
|
|
|
|
ARM DDI 0147D |
© Copyright ARM Limited 1999. All rights reserved. |
3-3 |