AMBA Test Methodology

6.7The ASB test interface controller

Figure 6-9 shows the ASB test interface controller state diagram.

TREQA & !TREQB

TURNAROUND

TREQA &

TREQB

Figure 6-9 Test interface controller state diagram

TREQA and TREQB are sampled on the falling edge of TCLK when TACK is HIGH, except in the NORMAL OPERATION state where TREQA is used asynchronously to transition into the ADDRESS OR CONTROL state. The reset state is NORMAL OPERATION.

6.7.1Control vector bit definitions

A control vector is included within the TIC to determine the types of transfer it can perform. The control vector is used to set the values of BSIZE, BPROT and BLOK and to control address incrementing.

Byte 0 of the control packet is used to define the access that will occur on the internal system bus. Byte 1 of the control packet is reserved for clock control and debug.

Table 6-4 shows the control vector bit assignments.

AMBA Test Methodology

Table 6-4 Control vector bit definitions